1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "tegra20-tamonten.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun model = "Avionic Design Plutux board"; 8*4882a593Smuzhiyun compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun host1x@50000000 { 11*4882a593Smuzhiyun hdmi@54280000 { 12*4882a593Smuzhiyun status = "okay"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun i2c@7000c000 { 17*4882a593Smuzhiyun wm8903: wm8903@1a { 18*4882a593Smuzhiyun compatible = "wlf,wm8903"; 19*4882a593Smuzhiyun reg = <0x1a>; 20*4882a593Smuzhiyun interrupt-parent = <&gpio>; 21*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun #gpio-cells = <2>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun micdet-cfg = <0>; 27*4882a593Smuzhiyun micdet-delay = <100>; 28*4882a593Smuzhiyun gpio-cfg = <0xffffffff 29*4882a593Smuzhiyun 0xffffffff 30*4882a593Smuzhiyun 0 31*4882a593Smuzhiyun 0xffffffff 32*4882a593Smuzhiyun 0xffffffff>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun sound { 37*4882a593Smuzhiyun compatible = "ad,tegra-audio-plutux", 38*4882a593Smuzhiyun "nvidia,tegra-audio-wm8903"; 39*4882a593Smuzhiyun nvidia,model = "Avionic Design Plutux"; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun nvidia,audio-routing = 42*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 43*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 44*4882a593Smuzhiyun "Int Spk", "ROP", 45*4882a593Smuzhiyun "Int Spk", "RON", 46*4882a593Smuzhiyun "Int Spk", "LOP", 47*4882a593Smuzhiyun "Int Spk", "LON", 48*4882a593Smuzhiyun "Mic Jack", "MICBIAS", 49*4882a593Smuzhiyun "IN1L", "Mic Jack"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 52*4882a593Smuzhiyun nvidia,audio-codec = <&wm8903>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 55*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 58*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 59*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 60*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun vcc_24v_reg: regulator@100 { 64*4882a593Smuzhiyun compatible = "regulator-fixed"; 65*4882a593Smuzhiyun regulator-name = "vcc_24v"; 66*4882a593Smuzhiyun regulator-min-microvolt = <24000000>; 67*4882a593Smuzhiyun regulator-max-microvolt = <24000000>; 68*4882a593Smuzhiyun regulator-always-on; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun vdd_5v0_reg: regulator@101 { 72*4882a593Smuzhiyun compatible = "regulator-fixed"; 73*4882a593Smuzhiyun regulator-name = "vdd_5v0"; 74*4882a593Smuzhiyun vin-supply = <&vcc_24v_reg>; 75*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 77*4882a593Smuzhiyun regulator-always-on; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun vdd_3v3_reg: regulator@102 { 81*4882a593Smuzhiyun compatible = "regulator-fixed"; 82*4882a593Smuzhiyun regulator-name = "vdd_3v3"; 83*4882a593Smuzhiyun vin-supply = <&vcc_24v_reg>; 84*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 86*4882a593Smuzhiyun regulator-always-on; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun vdd_1v8_reg: regulator@103 { 90*4882a593Smuzhiyun compatible = "regulator-fixed"; 91*4882a593Smuzhiyun regulator-name = "vdd_1v8"; 92*4882a593Smuzhiyun vin-supply = <&vdd_3v3_reg>; 93*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 94*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 95*4882a593Smuzhiyun regulator-always-on; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98