1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra114.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "NVIDIA SHIELD"; 9*4882a593Smuzhiyun compatible = "nvidia,roth", "nvidia,tegra114"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun /* SHIELD's bootloader's arguments need to be overridden */ 13*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; 14*4882a593Smuzhiyun /* SHIELD's bootloader will place initrd at this address */ 15*4882a593Smuzhiyun linux,initrd-start = <0x82000000>; 16*4882a593Smuzhiyun linux,initrd-end = <0x82800000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun serial0 = &uartd; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun firmware { 24*4882a593Smuzhiyun trusted-foundations { 25*4882a593Smuzhiyun compatible = "tlm,trusted-foundations"; 26*4882a593Smuzhiyun tlm,version-major = <2>; 27*4882a593Smuzhiyun tlm,version-minor = <8>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun memory@80000000 { 32*4882a593Smuzhiyun /* memory >= 0x79600000 is reserved for firmware usage */ 33*4882a593Smuzhiyun reg = <0x80000000 0x79600000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun host1x@50000000 { 37*4882a593Smuzhiyun dsi@54300000 { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun avdd-dsi-csi-supply = <&vdd_1v2_ap>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun panel@0 { 43*4882a593Smuzhiyun compatible = "lg,lh500wx1-sd03"; 44*4882a593Smuzhiyun reg = <0>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun power-supply = <&vdd_lcd>; 47*4882a593Smuzhiyun backlight = <&backlight>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pinmux@70000868 { 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun state_default: pinmux { 57*4882a593Smuzhiyun clk1_out_pw4 { 58*4882a593Smuzhiyun nvidia,pins = "clk1_out_pw4"; 59*4882a593Smuzhiyun nvidia,function = "extperiph1"; 60*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 61*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 62*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun dap1_din_pn1 { 65*4882a593Smuzhiyun nvidia,pins = "dap1_din_pn1"; 66*4882a593Smuzhiyun nvidia,function = "i2s0"; 67*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 68*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 69*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun dap1_dout_pn2 { 72*4882a593Smuzhiyun nvidia,pins = "dap1_dout_pn2", 73*4882a593Smuzhiyun "dap1_fs_pn0", 74*4882a593Smuzhiyun "dap1_sclk_pn3"; 75*4882a593Smuzhiyun nvidia,function = "i2s0"; 76*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 77*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 78*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun dap2_din_pa4 { 81*4882a593Smuzhiyun nvidia,pins = "dap2_din_pa4"; 82*4882a593Smuzhiyun nvidia,function = "i2s1"; 83*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 84*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 85*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun dap2_dout_pa5 { 88*4882a593Smuzhiyun nvidia,pins = "dap2_dout_pa5", 89*4882a593Smuzhiyun "dap2_fs_pa2", 90*4882a593Smuzhiyun "dap2_sclk_pa3"; 91*4882a593Smuzhiyun nvidia,function = "i2s1"; 92*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 93*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 94*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun dap4_din_pp5 { 97*4882a593Smuzhiyun nvidia,pins = "dap4_din_pp5", 98*4882a593Smuzhiyun "dap4_dout_pp6", 99*4882a593Smuzhiyun "dap4_fs_pp4", 100*4882a593Smuzhiyun "dap4_sclk_pp7"; 101*4882a593Smuzhiyun nvidia,function = "i2s3"; 102*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 103*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 104*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun dvfs_pwm_px0 { 107*4882a593Smuzhiyun nvidia,pins = "dvfs_pwm_px0", 108*4882a593Smuzhiyun "dvfs_clk_px2"; 109*4882a593Smuzhiyun nvidia,function = "cldvfs"; 110*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 111*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 112*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun ulpi_clk_py0 { 115*4882a593Smuzhiyun nvidia,pins = "ulpi_clk_py0", 116*4882a593Smuzhiyun "ulpi_data0_po1", 117*4882a593Smuzhiyun "ulpi_data1_po2", 118*4882a593Smuzhiyun "ulpi_data2_po3", 119*4882a593Smuzhiyun "ulpi_data3_po4", 120*4882a593Smuzhiyun "ulpi_data4_po5", 121*4882a593Smuzhiyun "ulpi_data5_po6", 122*4882a593Smuzhiyun "ulpi_data6_po7", 123*4882a593Smuzhiyun "ulpi_data7_po0"; 124*4882a593Smuzhiyun nvidia,function = "ulpi"; 125*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 126*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 127*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun ulpi_dir_py1 { 130*4882a593Smuzhiyun nvidia,pins = "ulpi_dir_py1", 131*4882a593Smuzhiyun "ulpi_nxt_py2"; 132*4882a593Smuzhiyun nvidia,function = "ulpi"; 133*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 134*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 135*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun ulpi_stp_py3 { 138*4882a593Smuzhiyun nvidia,pins = "ulpi_stp_py3"; 139*4882a593Smuzhiyun nvidia,function = "ulpi"; 140*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 141*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 142*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun cam_i2c_scl_pbb1 { 145*4882a593Smuzhiyun nvidia,pins = "cam_i2c_scl_pbb1", 146*4882a593Smuzhiyun "cam_i2c_sda_pbb2"; 147*4882a593Smuzhiyun nvidia,function = "i2c3"; 148*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 150*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 151*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 152*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun cam_mclk_pcc0 { 155*4882a593Smuzhiyun nvidia,pins = "cam_mclk_pcc0", 156*4882a593Smuzhiyun "pbb0"; 157*4882a593Smuzhiyun nvidia,function = "vi_alt3"; 158*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 159*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 160*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 161*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun pbb4 { 164*4882a593Smuzhiyun nvidia,pins = "pbb4"; 165*4882a593Smuzhiyun nvidia,function = "vgp4"; 166*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 168*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 169*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun gen2_i2c_scl_pt5 { 172*4882a593Smuzhiyun nvidia,pins = "gen2_i2c_scl_pt5", 173*4882a593Smuzhiyun "gen2_i2c_sda_pt6"; 174*4882a593Smuzhiyun nvidia,function = "i2c2"; 175*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 177*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 178*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 179*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun gmi_a16_pj7 { 182*4882a593Smuzhiyun nvidia,pins = "gmi_a16_pj7", 183*4882a593Smuzhiyun "gmi_a19_pk7"; 184*4882a593Smuzhiyun nvidia,function = "uartd"; 185*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 186*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 187*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun gmi_a17_pb0 { 190*4882a593Smuzhiyun nvidia,pins = "gmi_a17_pb0", 191*4882a593Smuzhiyun "gmi_a18_pb1"; 192*4882a593Smuzhiyun nvidia,function = "uartd"; 193*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 194*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 195*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun gmi_ad5_pg5 { 198*4882a593Smuzhiyun nvidia,pins = "gmi_ad5_pg5", 199*4882a593Smuzhiyun "gmi_wr_n_pi0"; 200*4882a593Smuzhiyun nvidia,function = "spi4"; 201*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 202*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 203*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun gmi_ad6_pg6 { 206*4882a593Smuzhiyun nvidia,pins = "gmi_ad6_pg6", 207*4882a593Smuzhiyun "gmi_ad7_pg7"; 208*4882a593Smuzhiyun nvidia,function = "spi4"; 209*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 210*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 211*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun gmi_ad12_ph4 { 214*4882a593Smuzhiyun nvidia,pins = "gmi_ad12_ph4"; 215*4882a593Smuzhiyun nvidia,function = "rsvd4"; 216*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 217*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 218*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun gmi_cs6_n_pi13 { 221*4882a593Smuzhiyun nvidia,pins = "gmi_cs6_n_pi3"; 222*4882a593Smuzhiyun nvidia,function = "nand"; 223*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 224*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 225*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun gmi_ad9_ph1 { 228*4882a593Smuzhiyun nvidia,pins = "gmi_ad9_ph1"; 229*4882a593Smuzhiyun nvidia,function = "pwm1"; 230*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 231*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 232*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun gmi_cs1_n_pj2 { 235*4882a593Smuzhiyun nvidia,pins = "gmi_cs1_n_pj2", 236*4882a593Smuzhiyun "gmi_oe_n_pi1"; 237*4882a593Smuzhiyun nvidia,function = "soc"; 238*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 239*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 240*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun gmi_rst_n_pi4 { 243*4882a593Smuzhiyun nvidia,pins = "gmi_rst_n_pi4"; 244*4882a593Smuzhiyun nvidia,function = "gmi"; 245*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 246*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 247*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun gmi_iordy_pi5 { 250*4882a593Smuzhiyun nvidia,pins = "gmi_iordy_pi5"; 251*4882a593Smuzhiyun nvidia,function = "gmi"; 252*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 253*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 254*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun clk2_out_pw5 { 257*4882a593Smuzhiyun nvidia,pins = "clk2_out_pw5"; 258*4882a593Smuzhiyun nvidia,function = "extperiph2"; 259*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 260*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 261*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun sdmmc1_clk_pz0 { 264*4882a593Smuzhiyun nvidia,pins = "sdmmc1_clk_pz0"; 265*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 266*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 267*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 268*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun sdmmc1_cmd_pz1 { 271*4882a593Smuzhiyun nvidia,pins = "sdmmc1_cmd_pz1", 272*4882a593Smuzhiyun "sdmmc1_dat0_py7", 273*4882a593Smuzhiyun "sdmmc1_dat1_py6", 274*4882a593Smuzhiyun "sdmmc1_dat2_py5", 275*4882a593Smuzhiyun "sdmmc1_dat3_py4"; 276*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 277*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 278*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 279*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun sdmmc3_clk_pa6 { 282*4882a593Smuzhiyun nvidia,pins = "sdmmc3_clk_pa6"; 283*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 284*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 285*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 286*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun sdmmc3_cmd_pa7 { 289*4882a593Smuzhiyun nvidia,pins = "sdmmc3_cmd_pa7", 290*4882a593Smuzhiyun "sdmmc3_dat0_pb7", 291*4882a593Smuzhiyun "sdmmc3_dat1_pb6", 292*4882a593Smuzhiyun "sdmmc3_dat2_pb5", 293*4882a593Smuzhiyun "sdmmc3_dat3_pb4", 294*4882a593Smuzhiyun "sdmmc3_cd_n_pv2", 295*4882a593Smuzhiyun "sdmmc3_clk_lb_out_pee4", 296*4882a593Smuzhiyun "sdmmc3_clk_lb_in_pee5"; 297*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 298*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 299*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 300*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun kb_col4_pq4 { 303*4882a593Smuzhiyun nvidia,pins = "kb_col4_pq4"; 304*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 305*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 306*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 307*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun sdmmc4_clk_pcc4 { 310*4882a593Smuzhiyun nvidia,pins = "sdmmc4_clk_pcc4"; 311*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 312*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 313*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 314*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun sdmmc4_cmd_pt7 { 317*4882a593Smuzhiyun nvidia,pins = "sdmmc4_cmd_pt7", 318*4882a593Smuzhiyun "sdmmc4_dat0_paa0", 319*4882a593Smuzhiyun "sdmmc4_dat1_paa1", 320*4882a593Smuzhiyun "sdmmc4_dat2_paa2", 321*4882a593Smuzhiyun "sdmmc4_dat3_paa3", 322*4882a593Smuzhiyun "sdmmc4_dat4_paa4", 323*4882a593Smuzhiyun "sdmmc4_dat5_paa5", 324*4882a593Smuzhiyun "sdmmc4_dat6_paa6", 325*4882a593Smuzhiyun "sdmmc4_dat7_paa7"; 326*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 327*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 328*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 329*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun clk_32k_out_pa0 { 332*4882a593Smuzhiyun nvidia,pins = "clk_32k_out_pa0"; 333*4882a593Smuzhiyun nvidia,function = "blink"; 334*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 335*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 336*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun kb_col0_pq0 { 339*4882a593Smuzhiyun nvidia,pins = "kb_col0_pq0", 340*4882a593Smuzhiyun "kb_col1_pq1", 341*4882a593Smuzhiyun "kb_col2_pq2", 342*4882a593Smuzhiyun "kb_row0_pr0", 343*4882a593Smuzhiyun "kb_row1_pr1", 344*4882a593Smuzhiyun "kb_row2_pr2", 345*4882a593Smuzhiyun "kb_row8_ps0"; 346*4882a593Smuzhiyun nvidia,function = "kbc"; 347*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 348*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 349*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun kb_row7_pr7 { 352*4882a593Smuzhiyun nvidia,pins = "kb_row7_pr7"; 353*4882a593Smuzhiyun nvidia,function = "rsvd2"; 354*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 355*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 356*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun kb_row10_ps2 { 359*4882a593Smuzhiyun nvidia,pins = "kb_row10_ps2"; 360*4882a593Smuzhiyun nvidia,function = "uarta"; 361*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 363*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun kb_row9_ps1 { 366*4882a593Smuzhiyun nvidia,pins = "kb_row9_ps1"; 367*4882a593Smuzhiyun nvidia,function = "uarta"; 368*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 369*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 370*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun pwr_i2c_scl_pz6 { 373*4882a593Smuzhiyun nvidia,pins = "pwr_i2c_scl_pz6", 374*4882a593Smuzhiyun "pwr_i2c_sda_pz7"; 375*4882a593Smuzhiyun nvidia,function = "i2cpwr"; 376*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 377*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 378*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 379*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 380*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun sys_clk_req_pz5 { 383*4882a593Smuzhiyun nvidia,pins = "sys_clk_req_pz5"; 384*4882a593Smuzhiyun nvidia,function = "sysclk"; 385*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 386*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 387*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun core_pwr_req { 390*4882a593Smuzhiyun nvidia,pins = "core_pwr_req"; 391*4882a593Smuzhiyun nvidia,function = "pwron"; 392*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 393*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 394*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun cpu_pwr_req { 397*4882a593Smuzhiyun nvidia,pins = "cpu_pwr_req"; 398*4882a593Smuzhiyun nvidia,function = "cpu"; 399*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 400*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 401*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun pwr_int_n { 404*4882a593Smuzhiyun nvidia,pins = "pwr_int_n"; 405*4882a593Smuzhiyun nvidia,function = "pmi"; 406*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 407*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 408*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun reset_out_n { 411*4882a593Smuzhiyun nvidia,pins = "reset_out_n"; 412*4882a593Smuzhiyun nvidia,function = "reset_out_n"; 413*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 414*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 415*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun clk3_out_pee0 { 418*4882a593Smuzhiyun nvidia,pins = "clk3_out_pee0"; 419*4882a593Smuzhiyun nvidia,function = "extperiph3"; 420*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 421*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 422*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun gen1_i2c_scl_pc4 { 425*4882a593Smuzhiyun nvidia,pins = "gen1_i2c_scl_pc4", 426*4882a593Smuzhiyun "gen1_i2c_sda_pc5"; 427*4882a593Smuzhiyun nvidia,function = "i2c1"; 428*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 429*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 430*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 431*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 432*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun uart2_cts_n_pj5 { 435*4882a593Smuzhiyun nvidia,pins = "uart2_cts_n_pj5"; 436*4882a593Smuzhiyun nvidia,function = "uartb"; 437*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 438*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 439*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun uart2_rts_n_pj6 { 442*4882a593Smuzhiyun nvidia,pins = "uart2_rts_n_pj6"; 443*4882a593Smuzhiyun nvidia,function = "uartb"; 444*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 445*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 446*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun uart2_rxd_pc3 { 449*4882a593Smuzhiyun nvidia,pins = "uart2_rxd_pc3"; 450*4882a593Smuzhiyun nvidia,function = "irda"; 451*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 452*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 453*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun uart2_txd_pc2 { 456*4882a593Smuzhiyun nvidia,pins = "uart2_txd_pc2"; 457*4882a593Smuzhiyun nvidia,function = "irda"; 458*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 459*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 460*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun uart3_cts_n_pa1 { 463*4882a593Smuzhiyun nvidia,pins = "uart3_cts_n_pa1", 464*4882a593Smuzhiyun "uart3_rxd_pw7"; 465*4882a593Smuzhiyun nvidia,function = "uartc"; 466*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 467*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 468*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun uart3_rts_n_pc0 { 471*4882a593Smuzhiyun nvidia,pins = "uart3_rts_n_pc0", 472*4882a593Smuzhiyun "uart3_txd_pw6"; 473*4882a593Smuzhiyun nvidia,function = "uartc"; 474*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 475*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 476*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun owr { 479*4882a593Smuzhiyun nvidia,pins = "owr"; 480*4882a593Smuzhiyun nvidia,function = "owr"; 481*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 482*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 483*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun hdmi_cec_pee3 { 486*4882a593Smuzhiyun nvidia,pins = "hdmi_cec_pee3"; 487*4882a593Smuzhiyun nvidia,function = "cec"; 488*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 489*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 490*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 491*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 492*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun ddc_scl_pv4 { 495*4882a593Smuzhiyun nvidia,pins = "ddc_scl_pv4", 496*4882a593Smuzhiyun "ddc_sda_pv5"; 497*4882a593Smuzhiyun nvidia,function = "i2c4"; 498*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 499*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 500*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 501*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 502*4882a593Smuzhiyun nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun spdif_in_pk6 { 505*4882a593Smuzhiyun nvidia,pins = "spdif_in_pk6"; 506*4882a593Smuzhiyun nvidia,function = "usb"; 507*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 508*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 509*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 510*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun usb_vbus_en0_pn4 { 513*4882a593Smuzhiyun nvidia,pins = "usb_vbus_en0_pn4"; 514*4882a593Smuzhiyun nvidia,function = "usb"; 515*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 516*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 517*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 518*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 519*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun gpio_x6_aud_px6 { 522*4882a593Smuzhiyun nvidia,pins = "gpio_x6_aud_px6"; 523*4882a593Smuzhiyun nvidia,function = "spi6"; 524*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 525*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 526*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun gpio_x1_aud_px1 { 529*4882a593Smuzhiyun nvidia,pins = "gpio_x1_aud_px1"; 530*4882a593Smuzhiyun nvidia,function = "rsvd2"; 531*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 532*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 533*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun gpio_x7_aud_px7 { 536*4882a593Smuzhiyun nvidia,pins = "gpio_x7_aud_px7"; 537*4882a593Smuzhiyun nvidia,function = "rsvd1"; 538*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 539*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 540*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun gmi_adv_n_pk0 { 543*4882a593Smuzhiyun nvidia,pins = "gmi_adv_n_pk0"; 544*4882a593Smuzhiyun nvidia,function = "gmi"; 545*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 546*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 547*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun gmi_cs0_n_pj0 { 550*4882a593Smuzhiyun nvidia,pins = "gmi_cs0_n_pj0"; 551*4882a593Smuzhiyun nvidia,function = "gmi"; 552*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 553*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 554*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 555*4882a593Smuzhiyun }; 556*4882a593Smuzhiyun pu3 { 557*4882a593Smuzhiyun nvidia,pins = "pu3"; 558*4882a593Smuzhiyun nvidia,function = "pwm0"; 559*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 560*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 561*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun gpio_x4_aud_px4 { 564*4882a593Smuzhiyun nvidia,pins = "gpio_x4_aud_px4", 565*4882a593Smuzhiyun "gpio_x5_aud_px5"; 566*4882a593Smuzhiyun nvidia,function = "rsvd1"; 567*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 568*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 569*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun gpio_x3_aud_px3 { 572*4882a593Smuzhiyun nvidia,pins = "gpio_x3_aud_px3"; 573*4882a593Smuzhiyun nvidia,function = "rsvd4"; 574*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 575*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 576*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun gpio_w2_aud_pw2 { 579*4882a593Smuzhiyun nvidia,pins = "gpio_w2_aud_pw2"; 580*4882a593Smuzhiyun nvidia,function = "rsvd2"; 581*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 582*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 583*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun gpio_w3_aud_pw3 { 586*4882a593Smuzhiyun nvidia,pins = "gpio_w3_aud_pw3"; 587*4882a593Smuzhiyun nvidia,function = "spi6"; 588*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 589*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 590*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 591*4882a593Smuzhiyun }; 592*4882a593Smuzhiyun dap3_fs_pp0 { 593*4882a593Smuzhiyun nvidia,pins = "dap3_fs_pp0", 594*4882a593Smuzhiyun "dap3_din_pp1", 595*4882a593Smuzhiyun "dap3_dout_pp2", 596*4882a593Smuzhiyun "dap3_sclk_pp3"; 597*4882a593Smuzhiyun nvidia,function = "i2s2"; 598*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 599*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 600*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 601*4882a593Smuzhiyun }; 602*4882a593Smuzhiyun pv0 { 603*4882a593Smuzhiyun nvidia,pins = "pv0"; 604*4882a593Smuzhiyun nvidia,function = "rsvd4"; 605*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 606*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 607*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun pv1 { 610*4882a593Smuzhiyun nvidia,pins = "pv1"; 611*4882a593Smuzhiyun nvidia,function = "rsvd1"; 612*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 614*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun pbb3 { 617*4882a593Smuzhiyun nvidia,pins = "pbb3", 618*4882a593Smuzhiyun "pbb5", 619*4882a593Smuzhiyun "pbb6", 620*4882a593Smuzhiyun "pbb7"; 621*4882a593Smuzhiyun nvidia,function = "rsvd4"; 622*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 623*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 624*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun pcc1 { 627*4882a593Smuzhiyun nvidia,pins = "pcc1", 628*4882a593Smuzhiyun "pcc2"; 629*4882a593Smuzhiyun nvidia,function = "rsvd4"; 630*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 631*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 632*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 633*4882a593Smuzhiyun }; 634*4882a593Smuzhiyun gmi_ad0_pg0 { 635*4882a593Smuzhiyun nvidia,pins = "gmi_ad0_pg0", 636*4882a593Smuzhiyun "gmi_ad1_pg1"; 637*4882a593Smuzhiyun nvidia,function = "gmi"; 638*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 639*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 640*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 641*4882a593Smuzhiyun }; 642*4882a593Smuzhiyun gmi_ad10_ph2 { 643*4882a593Smuzhiyun nvidia,pins = "gmi_ad10_ph2", 644*4882a593Smuzhiyun "gmi_ad12_ph4", 645*4882a593Smuzhiyun "gmi_ad15_ph7", 646*4882a593Smuzhiyun "gmi_cs3_n_pk4"; 647*4882a593Smuzhiyun nvidia,function = "gmi"; 648*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 649*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 650*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun gmi_ad11_ph3 { 653*4882a593Smuzhiyun nvidia,pins = "gmi_ad11_ph3", 654*4882a593Smuzhiyun "gmi_ad13_ph5", 655*4882a593Smuzhiyun "gmi_ad8_ph0", 656*4882a593Smuzhiyun "gmi_clk_pk1", 657*4882a593Smuzhiyun "gmi_cs2_n_pk3"; 658*4882a593Smuzhiyun nvidia,function = "gmi"; 659*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 660*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 661*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun gmi_ad14_ph6 { 664*4882a593Smuzhiyun nvidia,pins = "gmi_ad14_ph6", 665*4882a593Smuzhiyun "gmi_cs0_n_pj0", 666*4882a593Smuzhiyun "gmi_cs4_n_pk2", 667*4882a593Smuzhiyun "gmi_cs7_n_pi6", 668*4882a593Smuzhiyun "gmi_dqs_p_pj3", 669*4882a593Smuzhiyun "gmi_wp_n_pc7"; 670*4882a593Smuzhiyun nvidia,function = "gmi"; 671*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 672*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 673*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun gmi_ad2_pg2 { 676*4882a593Smuzhiyun nvidia,pins = "gmi_ad2_pg2", 677*4882a593Smuzhiyun "gmi_ad3_pg3"; 678*4882a593Smuzhiyun nvidia,function = "gmi"; 679*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 680*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 681*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun sdmmc1_wp_n_pv3 { 684*4882a593Smuzhiyun nvidia,pins = "sdmmc1_wp_n_pv3"; 685*4882a593Smuzhiyun nvidia,function = "spi4"; 686*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 687*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 688*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 689*4882a593Smuzhiyun }; 690*4882a593Smuzhiyun clk2_req_pcc5 { 691*4882a593Smuzhiyun nvidia,pins = "clk2_req_pcc5"; 692*4882a593Smuzhiyun nvidia,function = "rsvd4"; 693*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 694*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 695*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun kb_col3_pq3 { 698*4882a593Smuzhiyun nvidia,pins = "kb_col3_pq3"; 699*4882a593Smuzhiyun nvidia,function = "pwm2"; 700*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 701*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 702*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 703*4882a593Smuzhiyun }; 704*4882a593Smuzhiyun kb_col5_pq5 { 705*4882a593Smuzhiyun nvidia,pins = "kb_col5_pq5"; 706*4882a593Smuzhiyun nvidia,function = "kbc"; 707*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 708*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 709*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun kb_col6_pq6 { 712*4882a593Smuzhiyun nvidia,pins = "kb_col6_pq6", 713*4882a593Smuzhiyun "kb_col7_pq7"; 714*4882a593Smuzhiyun nvidia,function = "kbc"; 715*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 716*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 717*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun kb_row3_pr3 { 720*4882a593Smuzhiyun nvidia,pins = "kb_row3_pr3", 721*4882a593Smuzhiyun "kb_row4_pr4", 722*4882a593Smuzhiyun "kb_row6_pr6"; 723*4882a593Smuzhiyun nvidia,function = "kbc"; 724*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 725*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 726*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun clk3_req_pee1 { 729*4882a593Smuzhiyun nvidia,pins = "clk3_req_pee1"; 730*4882a593Smuzhiyun nvidia,function = "rsvd4"; 731*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 732*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 733*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun pu2 { 736*4882a593Smuzhiyun nvidia,pins = "pu2"; 737*4882a593Smuzhiyun nvidia,function = "rsvd1"; 738*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 739*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 740*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 741*4882a593Smuzhiyun }; 742*4882a593Smuzhiyun hdmi_int_pn7 { 743*4882a593Smuzhiyun nvidia,pins = "hdmi_int_pn7"; 744*4882a593Smuzhiyun nvidia,function = "rsvd1"; 745*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 746*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 747*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun drive_sdio1 { 751*4882a593Smuzhiyun nvidia,pins = "drive_sdio1"; 752*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 753*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 754*4882a593Smuzhiyun nvidia,pull-down-strength = <36>; 755*4882a593Smuzhiyun nvidia,pull-up-strength = <20>; 756*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 757*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun drive_sdio3 { 760*4882a593Smuzhiyun nvidia,pins = "drive_sdio3"; 761*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 762*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 763*4882a593Smuzhiyun nvidia,pull-down-strength = <36>; 764*4882a593Smuzhiyun nvidia,pull-up-strength = <20>; 765*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 766*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 767*4882a593Smuzhiyun }; 768*4882a593Smuzhiyun drive_gma { 769*4882a593Smuzhiyun nvidia,pins = "drive_gma"; 770*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 771*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 772*4882a593Smuzhiyun nvidia,pull-down-strength = <2>; 773*4882a593Smuzhiyun nvidia,pull-up-strength = <2>; 774*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 775*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 776*4882a593Smuzhiyun }; 777*4882a593Smuzhiyun }; 778*4882a593Smuzhiyun }; 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun /* Usable on reworked devices only */ 781*4882a593Smuzhiyun serial@70006300 { 782*4882a593Smuzhiyun status = "okay"; 783*4882a593Smuzhiyun }; 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun pwm@7000a000 { 786*4882a593Smuzhiyun status = "okay"; 787*4882a593Smuzhiyun }; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun i2c@7000d000 { 790*4882a593Smuzhiyun status = "okay"; 791*4882a593Smuzhiyun clock-frequency = <400000>; 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun regulator@43 { 794*4882a593Smuzhiyun compatible = "ti,tps51632"; 795*4882a593Smuzhiyun reg = <0x43>; 796*4882a593Smuzhiyun regulator-name = "vdd-cpu"; 797*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 798*4882a593Smuzhiyun regulator-max-microvolt = <1520000>; 799*4882a593Smuzhiyun regulator-always-on; 800*4882a593Smuzhiyun regulator-boot-on; 801*4882a593Smuzhiyun }; 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun palmas: pmic@58 { 804*4882a593Smuzhiyun compatible = "ti,palmas"; 805*4882a593Smuzhiyun reg = <0x58>; 806*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 807*4882a593Smuzhiyun 808*4882a593Smuzhiyun #interrupt-cells = <2>; 809*4882a593Smuzhiyun interrupt-controller; 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun ti,system-power-controller; 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun palmas_gpio: gpio { 814*4882a593Smuzhiyun compatible = "ti,palmas-gpio"; 815*4882a593Smuzhiyun gpio-controller; 816*4882a593Smuzhiyun #gpio-cells = <2>; 817*4882a593Smuzhiyun }; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun pmic { 820*4882a593Smuzhiyun compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun regulators { 823*4882a593Smuzhiyun smps12 { 824*4882a593Smuzhiyun regulator-name = "vdd-ddr"; 825*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 826*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 827*4882a593Smuzhiyun regulator-always-on; 828*4882a593Smuzhiyun regulator-boot-on; 829*4882a593Smuzhiyun }; 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun vdd_1v8: smps3 { 832*4882a593Smuzhiyun regulator-name = "vdd-1v8"; 833*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 834*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 835*4882a593Smuzhiyun regulator-boot-on; 836*4882a593Smuzhiyun }; 837*4882a593Smuzhiyun 838*4882a593Smuzhiyun smps457 { 839*4882a593Smuzhiyun regulator-name = "vdd-soc"; 840*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 841*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 842*4882a593Smuzhiyun regulator-always-on; 843*4882a593Smuzhiyun regulator-boot-on; 844*4882a593Smuzhiyun }; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun smps8 { 847*4882a593Smuzhiyun regulator-name = "avdd-pll-1v05"; 848*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 849*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 850*4882a593Smuzhiyun regulator-always-on; 851*4882a593Smuzhiyun regulator-boot-on; 852*4882a593Smuzhiyun }; 853*4882a593Smuzhiyun 854*4882a593Smuzhiyun smps9 { 855*4882a593Smuzhiyun regulator-name = "vdd-2v85-emmc"; 856*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 857*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 858*4882a593Smuzhiyun regulator-always-on; 859*4882a593Smuzhiyun }; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun smps10_out1 { 862*4882a593Smuzhiyun regulator-name = "vdd-fan"; 863*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 864*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 865*4882a593Smuzhiyun regulator-always-on; 866*4882a593Smuzhiyun regulator-boot-on; 867*4882a593Smuzhiyun }; 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun smps10_out2 { 870*4882a593Smuzhiyun regulator-name = "vdd-5v0-sys"; 871*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 872*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 873*4882a593Smuzhiyun regulator-always-on; 874*4882a593Smuzhiyun regulator-boot-on; 875*4882a593Smuzhiyun }; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun ldo2 { 878*4882a593Smuzhiyun regulator-name = "vdd-2v8-display"; 879*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 880*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 881*4882a593Smuzhiyun regulator-always-on; 882*4882a593Smuzhiyun regulator-boot-on; 883*4882a593Smuzhiyun }; 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun vdd_1v2_ap: ldo3 { 886*4882a593Smuzhiyun regulator-name = "avdd-1v2"; 887*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 888*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 889*4882a593Smuzhiyun regulator-always-on; 890*4882a593Smuzhiyun regulator-boot-on; 891*4882a593Smuzhiyun }; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun ldo4 { 894*4882a593Smuzhiyun regulator-name = "vpp-fuse"; 895*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 896*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 897*4882a593Smuzhiyun }; 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun ldo5 { 900*4882a593Smuzhiyun regulator-name = "avdd-hdmi-pll"; 901*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 902*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 903*4882a593Smuzhiyun }; 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun ldo6 { 906*4882a593Smuzhiyun regulator-name = "vdd-sensor-2v8"; 907*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 908*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 909*4882a593Smuzhiyun }; 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun ldo8 { 912*4882a593Smuzhiyun regulator-name = "vdd-rtc"; 913*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 914*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 915*4882a593Smuzhiyun regulator-always-on; 916*4882a593Smuzhiyun regulator-boot-on; 917*4882a593Smuzhiyun ti,enable-ldo8-tracking; 918*4882a593Smuzhiyun }; 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun vddio_sdmmc3: ldo9 { 921*4882a593Smuzhiyun regulator-name = "vddio-sdmmc3"; 922*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 923*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 924*4882a593Smuzhiyun }; 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun ldousb { 927*4882a593Smuzhiyun regulator-name = "avdd-usb-hdmi"; 928*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 929*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 930*4882a593Smuzhiyun regulator-always-on; 931*4882a593Smuzhiyun regulator-boot-on; 932*4882a593Smuzhiyun }; 933*4882a593Smuzhiyun 934*4882a593Smuzhiyun vdd_3v3_sys: regen1 { 935*4882a593Smuzhiyun regulator-name = "rail-3v3"; 936*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 937*4882a593Smuzhiyun regulator-always-on; 938*4882a593Smuzhiyun regulator-boot-on; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun regen2 { 942*4882a593Smuzhiyun regulator-name = "rail-5v0"; 943*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 944*4882a593Smuzhiyun regulator-always-on; 945*4882a593Smuzhiyun regulator-boot-on; 946*4882a593Smuzhiyun }; 947*4882a593Smuzhiyun 948*4882a593Smuzhiyun }; 949*4882a593Smuzhiyun }; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun rtc { 952*4882a593Smuzhiyun compatible = "ti,palmas-rtc"; 953*4882a593Smuzhiyun interrupt-parent = <&palmas>; 954*4882a593Smuzhiyun interrupts = <8 0>; 955*4882a593Smuzhiyun }; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun }; 958*4882a593Smuzhiyun }; 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun pmc@7000e400 { 961*4882a593Smuzhiyun nvidia,invert-interrupt; 962*4882a593Smuzhiyun }; 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun /* SD card */ 965*4882a593Smuzhiyun mmc@78000400 { 966*4882a593Smuzhiyun status = "okay"; 967*4882a593Smuzhiyun bus-width = <4>; 968*4882a593Smuzhiyun vqmmc-supply = <&vddio_sdmmc3>; 969*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 970*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 971*4882a593Smuzhiyun }; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun /* eMMC */ 974*4882a593Smuzhiyun mmc@78000600 { 975*4882a593Smuzhiyun status = "okay"; 976*4882a593Smuzhiyun bus-width = <8>; 977*4882a593Smuzhiyun non-removable; 978*4882a593Smuzhiyun }; 979*4882a593Smuzhiyun 980*4882a593Smuzhiyun /* External USB port (must be powered) */ 981*4882a593Smuzhiyun usb@7d000000 { 982*4882a593Smuzhiyun status = "okay"; 983*4882a593Smuzhiyun }; 984*4882a593Smuzhiyun 985*4882a593Smuzhiyun usb-phy@7d000000 { 986*4882a593Smuzhiyun status = "okay"; 987*4882a593Smuzhiyun nvidia,xcvr-setup = <7>; 988*4882a593Smuzhiyun nvidia,xcvr-lsfslew = <2>; 989*4882a593Smuzhiyun nvidia,xcvr-lsrslew = <2>; 990*4882a593Smuzhiyun interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 991*4882a593Smuzhiyun /* Should be changed to "otg" once we have vbus_supply */ 992*4882a593Smuzhiyun /* As of now, USB devices need to be powered externally */ 993*4882a593Smuzhiyun dr_mode = "host"; 994*4882a593Smuzhiyun }; 995*4882a593Smuzhiyun 996*4882a593Smuzhiyun /* SHIELD controller */ 997*4882a593Smuzhiyun usb@7d008000 { 998*4882a593Smuzhiyun status = "okay"; 999*4882a593Smuzhiyun }; 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun usb-phy@7d008000 { 1002*4882a593Smuzhiyun status = "okay"; 1003*4882a593Smuzhiyun nvidia,xcvr-setup = <7>; 1004*4882a593Smuzhiyun nvidia,xcvr-lsfslew = <2>; 1005*4882a593Smuzhiyun nvidia,xcvr-lsrslew = <2>; 1006*4882a593Smuzhiyun }; 1007*4882a593Smuzhiyun 1008*4882a593Smuzhiyun backlight: backlight { 1009*4882a593Smuzhiyun compatible = "pwm-backlight"; 1010*4882a593Smuzhiyun pwms = <&pwm 1 40000>; 1011*4882a593Smuzhiyun 1012*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 1013*4882a593Smuzhiyun default-brightness-level = <6>; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun power-supply = <&lcd_bl_en>; 1016*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1017*4882a593Smuzhiyun }; 1018*4882a593Smuzhiyun 1019*4882a593Smuzhiyun clk32k_in: clock@0 { 1020*4882a593Smuzhiyun compatible = "fixed-clock"; 1021*4882a593Smuzhiyun clock-frequency = <32768>; 1022*4882a593Smuzhiyun #clock-cells = <0>; 1023*4882a593Smuzhiyun }; 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun gpio-keys { 1026*4882a593Smuzhiyun compatible = "gpio-keys"; 1027*4882a593Smuzhiyun 1028*4882a593Smuzhiyun back { 1029*4882a593Smuzhiyun label = "Back"; 1030*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1031*4882a593Smuzhiyun linux,code = <KEY_BACK>; 1032*4882a593Smuzhiyun }; 1033*4882a593Smuzhiyun 1034*4882a593Smuzhiyun home { 1035*4882a593Smuzhiyun label = "Home"; 1036*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1037*4882a593Smuzhiyun linux,code = <KEY_HOME>; 1038*4882a593Smuzhiyun }; 1039*4882a593Smuzhiyun 1040*4882a593Smuzhiyun power { 1041*4882a593Smuzhiyun label = "Power"; 1042*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1043*4882a593Smuzhiyun linux,code = <KEY_POWER>; 1044*4882a593Smuzhiyun wakeup-source; 1045*4882a593Smuzhiyun }; 1046*4882a593Smuzhiyun }; 1047*4882a593Smuzhiyun 1048*4882a593Smuzhiyun lcd_bl_en: regulator@0 { 1049*4882a593Smuzhiyun compatible = "regulator-fixed"; 1050*4882a593Smuzhiyun regulator-name = "lcd_bl_en"; 1051*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1052*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1053*4882a593Smuzhiyun regulator-boot-on; 1054*4882a593Smuzhiyun }; 1055*4882a593Smuzhiyun 1056*4882a593Smuzhiyun vdd_lcd: regulator@1 { 1057*4882a593Smuzhiyun compatible = "regulator-fixed"; 1058*4882a593Smuzhiyun regulator-name = "vdd_lcd_1v8"; 1059*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1060*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1061*4882a593Smuzhiyun vin-supply = <&vdd_1v8>; 1062*4882a593Smuzhiyun enable-active-high; 1063*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 1064*4882a593Smuzhiyun regulator-boot-on; 1065*4882a593Smuzhiyun }; 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun regulator@2 { 1068*4882a593Smuzhiyun compatible = "regulator-fixed"; 1069*4882a593Smuzhiyun regulator-name = "vdd_1v8_ts"; 1070*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1071*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1072*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; 1073*4882a593Smuzhiyun regulator-boot-on; 1074*4882a593Smuzhiyun }; 1075*4882a593Smuzhiyun 1076*4882a593Smuzhiyun regulator@3 { 1077*4882a593Smuzhiyun compatible = "regulator-fixed"; 1078*4882a593Smuzhiyun regulator-name = "vdd_3v3_ts"; 1079*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1080*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1081*4882a593Smuzhiyun enable-active-high; 1082*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; 1083*4882a593Smuzhiyun regulator-boot-on; 1084*4882a593Smuzhiyun }; 1085*4882a593Smuzhiyun 1086*4882a593Smuzhiyun regulator@4 { 1087*4882a593Smuzhiyun compatible = "regulator-fixed"; 1088*4882a593Smuzhiyun regulator-name = "vdd_1v8_com"; 1089*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1090*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1091*4882a593Smuzhiyun vin-supply = <&vdd_1v8>; 1092*4882a593Smuzhiyun enable-active-high; 1093*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 1094*4882a593Smuzhiyun regulator-boot-on; 1095*4882a593Smuzhiyun }; 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun regulator@5 { 1098*4882a593Smuzhiyun compatible = "regulator-fixed"; 1099*4882a593Smuzhiyun regulator-name = "vdd_3v3_com"; 1100*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1101*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1102*4882a593Smuzhiyun vin-supply = <&vdd_3v3_sys>; 1103*4882a593Smuzhiyun enable-active-high; 1104*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; 1105*4882a593Smuzhiyun regulator-always-on; 1106*4882a593Smuzhiyun regulator-boot-on; 1107*4882a593Smuzhiyun }; 1108*4882a593Smuzhiyun}; 1109