1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "sunxi-bananapi-m2-plus.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * Bananapi M2+ v1.2 uses a GPIO line to change the effective 11*4882a593Smuzhiyun * resistance on the CPU regulator's feedback pin. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun reg_vdd_cpux: vdd-cpux { 14*4882a593Smuzhiyun compatible = "regulator-gpio"; 15*4882a593Smuzhiyun regulator-name = "vdd-cpux"; 16*4882a593Smuzhiyun regulator-type = "voltage"; 17*4882a593Smuzhiyun regulator-boot-on; 18*4882a593Smuzhiyun regulator-always-on; 19*4882a593Smuzhiyun regulator-min-microvolt = <1108475>; 20*4882a593Smuzhiyun regulator-max-microvolt = <1308475>; 21*4882a593Smuzhiyun regulator-ramp-delay = <50>; /* 4ms */ 22*4882a593Smuzhiyun gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ 23*4882a593Smuzhiyun gpios-states = <0x1>; 24*4882a593Smuzhiyun states = <1108475 0>, <1308475 1>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&cpu0 { 29*4882a593Smuzhiyun cpu-supply = <®_vdd_cpux>; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&cpu1 { 33*4882a593Smuzhiyun cpu-supply = <®_vdd_cpux>; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&cpu2 { 37*4882a593Smuzhiyun cpu-supply = <®_vdd_cpux>; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&cpu3 { 41*4882a593Smuzhiyun cpu-supply = <®_vdd_cpux>; 42*4882a593Smuzhiyun}; 43