1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 4*4882a593Smuzhiyun * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "stm32mp153.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun soc { 11*4882a593Smuzhiyun gpu: gpu@59000000 { 12*4882a593Smuzhiyun compatible = "vivante,gc"; 13*4882a593Smuzhiyun reg = <0x59000000 0x800>; 14*4882a593Smuzhiyun interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 15*4882a593Smuzhiyun clocks = <&rcc GPU>, <&rcc GPU_K>; 16*4882a593Smuzhiyun clock-names = "bus" ,"core"; 17*4882a593Smuzhiyun resets = <&rcc GPU_R>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun dsi: dsi@5a000000 { 21*4882a593Smuzhiyun compatible = "st,stm32-dsi"; 22*4882a593Smuzhiyun reg = <0x5a000000 0x800>; 23*4882a593Smuzhiyun clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; 24*4882a593Smuzhiyun clock-names = "pclk", "ref", "px_clk"; 25*4882a593Smuzhiyun resets = <&rcc DSI_R>; 26*4882a593Smuzhiyun reset-names = "apb"; 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun ports { 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <0>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38