1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2012 ST-Ericsson AB 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree for the HREF+ prior to the v60 variant. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "ste-href-ab8500.dtsi" 9*4882a593Smuzhiyun#include "ste-href.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun gpio_keys { 13*4882a593Smuzhiyun button@1 { 14*4882a593Smuzhiyun gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun soc { 19*4882a593Smuzhiyun /* Enable UART1 on this board */ 20*4882a593Smuzhiyun uart@80121000 { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun i2c@80004000 { 25*4882a593Smuzhiyun tps61052@33 { 26*4882a593Smuzhiyun compatible = "ti,tps61052"; 27*4882a593Smuzhiyun reg = <0x33>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun tc35892@42 { 31*4882a593Smuzhiyun compatible = "toshiba,tc35892"; 32*4882a593Smuzhiyun reg = <0x42>; 33*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 34*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_EDGE_RISING>; 35*4882a593Smuzhiyun pinctrl-names = "default"; 36*4882a593Smuzhiyun pinctrl-0 = <&tc35892_hrefprev60_mode>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun interrupt-controller; 39*4882a593Smuzhiyun #interrupt-cells = <1>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun tc3589x_gpio: tc3589x_gpio { 42*4882a593Smuzhiyun compatible = "tc3589x-gpio"; 43*4882a593Smuzhiyun interrupts = <0>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun interrupt-controller; 46*4882a593Smuzhiyun #interrupt-cells = <2>; 47*4882a593Smuzhiyun gpio-controller; 48*4882a593Smuzhiyun #gpio-cells = <2>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun spi@80002000 { 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * On the first generation boards, this SSP/SPI port was connected 56*4882a593Smuzhiyun * to the AB8500. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&ssp0_hrefprev60_mode>; 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun // External Micro SD slot 64*4882a593Smuzhiyun sdi0_per1@80126000 { 65*4882a593Smuzhiyun cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun vmmci: regulator-gpio { 69*4882a593Smuzhiyun gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; 70*4882a593Smuzhiyun enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; 71*4882a593Smuzhiyun enable-active-high; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun pinctrl { 75*4882a593Smuzhiyun /* Set this up using hogs */ 76*4882a593Smuzhiyun pinctrl-names = "default"; 77*4882a593Smuzhiyun pinctrl-0 = <&ipgpio_hrefprev60_mode>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun ssp0 { 80*4882a593Smuzhiyun ssp0_hrefprev60_mode: ssp0_hrefprev60_default { 81*4882a593Smuzhiyun hrefprev60_mux { 82*4882a593Smuzhiyun function = "ssp0"; 83*4882a593Smuzhiyun groups = "ssp0_a_1"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun hrefprev60_cfg1 { 86*4882a593Smuzhiyun pins = "GPIO145_C13"; /* RXD */ 87*4882a593Smuzhiyun ste,config = <&in_pd>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun sdi0 { 93*4882a593Smuzhiyun /* This additional pin needed on early MOP500 and HREFs previous to v60 */ 94*4882a593Smuzhiyun sdi0_default_mode: sdi0_default { 95*4882a593Smuzhiyun hrefprev60_mux { 96*4882a593Smuzhiyun function = "mc0"; 97*4882a593Smuzhiyun groups = "mc0dat31dir_a_1"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun hrefprev60_cfg1 { 100*4882a593Smuzhiyun pins = "GPIO21_AB3"; /* DAT31DIR */ 101*4882a593Smuzhiyun ste,config = <&out_hi>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun tc35892 { 107*4882a593Smuzhiyun tc35892_hrefprev60_mode: tc35892_hrefprev60 { 108*4882a593Smuzhiyun hrefprev60_cfg { 109*4882a593Smuzhiyun pins = "GPIO217_AH12"; 110*4882a593Smuzhiyun ste,config = <&gpio_in_pu>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun ipgpio { 115*4882a593Smuzhiyun ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { 116*4882a593Smuzhiyun hrefprev60_mux { 117*4882a593Smuzhiyun function = "ipgpio"; 118*4882a593Smuzhiyun groups = "ipgpio0_c_1", "ipgpio1_c_1"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun hrefprev60_cfg1 { 121*4882a593Smuzhiyun pins = "GPIO6_AF6", "GPIO7_AG5"; 122*4882a593Smuzhiyun ste,config = <&in_pu>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun}; 129