1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2012 ST-Ericsson AB 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 7*4882a593Smuzhiyun#include <dt-bindings/leds/common.h> 8*4882a593Smuzhiyun#include "ste-href-family-pinctrl.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun memory { 12*4882a593Smuzhiyun device_type = "memory"; 13*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun soc { 17*4882a593Smuzhiyun uart@80120000 { 18*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 19*4882a593Smuzhiyun pinctrl-0 = <&u0_a_1_default>; 20*4882a593Smuzhiyun pinctrl-1 = <&u0_a_1_sleep>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* This UART is unused and thus left disabled */ 25*4882a593Smuzhiyun uart@80121000 { 26*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 27*4882a593Smuzhiyun pinctrl-0 = <&u1rxtx_a_1_default>; 28*4882a593Smuzhiyun pinctrl-1 = <&u1rxtx_a_1_sleep>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uart@80007000 { 32*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 33*4882a593Smuzhiyun pinctrl-0 = <&u2rxtx_c_1_default>; 34*4882a593Smuzhiyun pinctrl-1 = <&u2rxtx_c_1_sleep>; 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun i2c@80004000 { 39*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 40*4882a593Smuzhiyun pinctrl-0 = <&i2c0_a_1_default>; 41*4882a593Smuzhiyun pinctrl-1 = <&i2c0_a_1_sleep>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun i2c@80122000 { 46*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 47*4882a593Smuzhiyun pinctrl-0 = <&i2c1_b_2_default>; 48*4882a593Smuzhiyun pinctrl-1 = <&i2c1_b_2_sleep>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun i2c@80128000 { 53*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 54*4882a593Smuzhiyun pinctrl-0 = <&i2c2_b_2_default>; 55*4882a593Smuzhiyun pinctrl-1 = <&i2c2_b_2_sleep>; 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun lp5521@33 { 58*4882a593Smuzhiyun compatible = "national,lp5521"; 59*4882a593Smuzhiyun reg = <0x33>; 60*4882a593Smuzhiyun label = "lp5521_pri"; 61*4882a593Smuzhiyun clock-mode = /bits/ 8 <2>; 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <0>; 64*4882a593Smuzhiyun chan@0 { 65*4882a593Smuzhiyun reg = <0>; 66*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 67*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 68*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 69*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun chan@1 { 72*4882a593Smuzhiyun reg = <1>; 73*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 74*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 75*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun chan@2 { 78*4882a593Smuzhiyun reg = <2>; 79*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 80*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 81*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun lp5521@34 { 85*4882a593Smuzhiyun compatible = "national,lp5521"; 86*4882a593Smuzhiyun reg = <0x34>; 87*4882a593Smuzhiyun label = "lp5521_sec"; 88*4882a593Smuzhiyun clock-mode = /bits/ 8 <2>; 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun chan@0 { 92*4882a593Smuzhiyun reg = <0>; 93*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 94*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 95*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun chan@1 { 98*4882a593Smuzhiyun reg = <1>; 99*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 100*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 101*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun chan@2 { 104*4882a593Smuzhiyun reg = <2>; 105*4882a593Smuzhiyun led-cur = /bits/ 8 <0x2f>; 106*4882a593Smuzhiyun max-cur = /bits/ 8 <0x5f>; 107*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun bh1780@29 { 111*4882a593Smuzhiyun compatible = "rohm,bh1780gli"; 112*4882a593Smuzhiyun reg = <0x29>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun i2c@80110000 { 117*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 118*4882a593Smuzhiyun pinctrl-0 = <&i2c3_c_2_default>; 119*4882a593Smuzhiyun pinctrl-1 = <&i2c3_c_2_sleep>; 120*4882a593Smuzhiyun status = "okay"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* ST6G3244ME level translator for 1.8/2.9 V */ 124*4882a593Smuzhiyun vmmci: regulator-gpio { 125*4882a593Smuzhiyun compatible = "regulator-gpio"; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 128*4882a593Smuzhiyun regulator-max-microvolt = <2900000>; 129*4882a593Smuzhiyun regulator-name = "mmci-reg"; 130*4882a593Smuzhiyun regulator-type = "voltage"; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun startup-delay-us = <100>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun states = <1800000 0x1 135*4882a593Smuzhiyun 2900000 0x0>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun // External Micro SD slot 139*4882a593Smuzhiyun sdi0_per1@80126000 { 140*4882a593Smuzhiyun arm,primecell-periphid = <0x10480180>; 141*4882a593Smuzhiyun max-frequency = <100000000>; 142*4882a593Smuzhiyun bus-width = <4>; 143*4882a593Smuzhiyun cap-sd-highspeed; 144*4882a593Smuzhiyun cap-mmc-highspeed; 145*4882a593Smuzhiyun sd-uhs-sdr12; 146*4882a593Smuzhiyun sd-uhs-sdr25; 147*4882a593Smuzhiyun full-pwr-cycle; 148*4882a593Smuzhiyun st,sig-dir-dat0; 149*4882a593Smuzhiyun st,sig-dir-dat2; 150*4882a593Smuzhiyun st,sig-dir-cmd; 151*4882a593Smuzhiyun st,sig-pin-fbclk; 152*4882a593Smuzhiyun vmmc-supply = <&ab8500_ldo_aux3_reg>; 153*4882a593Smuzhiyun vqmmc-supply = <&vmmci>; 154*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 155*4882a593Smuzhiyun pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; 156*4882a593Smuzhiyun pinctrl-1 = <&mc0_a_1_sleep>; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun status = "okay"; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun // WLAN SDIO channel 162*4882a593Smuzhiyun sdi1_per2@80118000 { 163*4882a593Smuzhiyun arm,primecell-periphid = <0x10480180>; 164*4882a593Smuzhiyun max-frequency = <100000000>; 165*4882a593Smuzhiyun bus-width = <4>; 166*4882a593Smuzhiyun non-removable; 167*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 168*4882a593Smuzhiyun pinctrl-0 = <&mc1_a_1_default>; 169*4882a593Smuzhiyun pinctrl-1 = <&mc1_a_1_sleep>; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun // PoP:ed eMMC 175*4882a593Smuzhiyun sdi2_per3@80005000 { 176*4882a593Smuzhiyun arm,primecell-periphid = <0x10480180>; 177*4882a593Smuzhiyun max-frequency = <100000000>; 178*4882a593Smuzhiyun bus-width = <8>; 179*4882a593Smuzhiyun cap-mmc-highspeed; 180*4882a593Smuzhiyun non-removable; 181*4882a593Smuzhiyun vmmc-supply = <&db8500_vsmps2_reg>; 182*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 183*4882a593Smuzhiyun pinctrl-0 = <&mc2_a_1_default>; 184*4882a593Smuzhiyun pinctrl-1 = <&mc2_a_1_sleep>; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun status = "okay"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun // On-board eMMC 190*4882a593Smuzhiyun sdi4_per2@80114000 { 191*4882a593Smuzhiyun arm,primecell-periphid = <0x10480180>; 192*4882a593Smuzhiyun max-frequency = <100000000>; 193*4882a593Smuzhiyun bus-width = <8>; 194*4882a593Smuzhiyun cap-mmc-highspeed; 195*4882a593Smuzhiyun non-removable; 196*4882a593Smuzhiyun vmmc-supply = <&ab8500_ldo_aux2_reg>; 197*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 198*4882a593Smuzhiyun pinctrl-0 = <&mc4_a_1_default>; 199*4882a593Smuzhiyun pinctrl-1 = <&mc4_a_1_sleep>; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun msp0: msp@80123000 { 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun pinctrl-0 = <&msp0txrxtfstck_a_1_default>; 207*4882a593Smuzhiyun status = "okay"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun msp1: msp@80124000 { 211*4882a593Smuzhiyun pinctrl-names = "default"; 212*4882a593Smuzhiyun pinctrl-0 = <&msp1txrx_a_1_default>; 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun msp2: msp@80117000 { 217*4882a593Smuzhiyun pinctrl-names = "default"; 218*4882a593Smuzhiyun pinctrl-0 = <&msp2_a_1_default>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun msp3: msp@80125000 { 222*4882a593Smuzhiyun status = "okay"; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun prcmu@80157000 { 226*4882a593Smuzhiyun ab8500 { 227*4882a593Smuzhiyun ab8500-gpiocontroller { 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun ab8500_usb { 231*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 232*4882a593Smuzhiyun pinctrl-0 = <&usb_a_1_default>; 233*4882a593Smuzhiyun pinctrl-1 = <&usb_a_1_sleep>; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun ab8500-regulators { 237*4882a593Smuzhiyun ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 238*4882a593Smuzhiyun regulator-name = "V-DISPLAY"; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { 242*4882a593Smuzhiyun regulator-name = "V-eMMC1"; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { 246*4882a593Smuzhiyun regulator-name = "V-MMC-SD"; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun ab8500_ldo_intcore_reg: ab8500_ldo_intcore { 250*4882a593Smuzhiyun regulator-name = "V-INTCORE"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun ab8500_ldo_tvout_reg: ab8500_ldo_tvout { 254*4882a593Smuzhiyun regulator-name = "V-TVOUT"; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun ab8500_ldo_audio_reg: ab8500_ldo_audio { 258*4882a593Smuzhiyun regulator-name = "V-AUD"; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { 262*4882a593Smuzhiyun regulator-name = "V-AMIC1"; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { 266*4882a593Smuzhiyun regulator-name = "V-AMIC2"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun ab8500_ldo_dmic_reg: ab8500_ldo_dmic { 270*4882a593Smuzhiyun regulator-name = "V-DMIC"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun ab8500_ldo_ana_reg: ab8500_ldo_ana { 274*4882a593Smuzhiyun regulator-name = "V-CSI/DSI"; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun pinctrl { 281*4882a593Smuzhiyun sdi0 { 282*4882a593Smuzhiyun sdi0_default_mode: sdi0_default { 283*4882a593Smuzhiyun /* Some boards set additional settings here */ 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun mcde@a0350000 { 289*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 290*4882a593Smuzhiyun pinctrl-0 = <&lcd_default_mode>; 291*4882a593Smuzhiyun pinctrl-1 = <&lcd_sleep_mode>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun}; 295