xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Linaro Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include "ste-dbx5x0-pinctrl.dtsi"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	soc {
10*4882a593Smuzhiyun		pinctrl {
11*4882a593Smuzhiyun			/* Settings for all SPI default and sleep states */
12*4882a593Smuzhiyun			spi2 {
13*4882a593Smuzhiyun				spi2_default_mode: spi_default {
14*4882a593Smuzhiyun					default_mux {
15*4882a593Smuzhiyun						function = "spi2";
16*4882a593Smuzhiyun						groups = "spi2_oc1_2";
17*4882a593Smuzhiyun					};
18*4882a593Smuzhiyun					default_cfg1 {
19*4882a593Smuzhiyun						pins = "GPIO216_AG12"; /* FRM */
20*4882a593Smuzhiyun						ste,config = <&gpio_out_hi>;
21*4882a593Smuzhiyun					};
22*4882a593Smuzhiyun					default_cfg2 {
23*4882a593Smuzhiyun						pins = "GPIO218_AH11"; /* RXD */
24*4882a593Smuzhiyun						ste,config = <&in_pd>;
25*4882a593Smuzhiyun					};
26*4882a593Smuzhiyun					default_cfg3 {
27*4882a593Smuzhiyun						pins =
28*4882a593Smuzhiyun						"GPIO215_AH13", /* TXD */
29*4882a593Smuzhiyun						"GPIO217_AH12"; /* CLK */
30*4882a593Smuzhiyun						ste,config = <&out_lo>;
31*4882a593Smuzhiyun					};
32*4882a593Smuzhiyun				};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun				spi2_idle_mode: spi_idle {
35*4882a593Smuzhiyun					/*
36*4882a593Smuzhiyun					 * The idle mode is basically sleep mode sans wakeups. Also
37*4882a593Smuzhiyun					 * note that we have muxes the pins off the function here
38*4882a593Smuzhiyun					 * as we do not state any muxing.
39*4882a593Smuzhiyun					 */
40*4882a593Smuzhiyun					idle_cfg1 {
41*4882a593Smuzhiyun						pins = "GPIO218_AH11"; /* RXD */
42*4882a593Smuzhiyun						ste,config = <&slpm_in_pdis>;
43*4882a593Smuzhiyun					};
44*4882a593Smuzhiyun					idle_cfg2 {
45*4882a593Smuzhiyun						pins = "GPIO215_AH13"; /* TXD */
46*4882a593Smuzhiyun						ste,config = <&slpm_out_lo_pdis>;
47*4882a593Smuzhiyun					};
48*4882a593Smuzhiyun					idle_cfg3 {
49*4882a593Smuzhiyun						pins = "GPIO217_AH12"; /* CLK */
50*4882a593Smuzhiyun						ste,config = <&slpm_pdis>;
51*4882a593Smuzhiyun					};
52*4882a593Smuzhiyun				};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun				spi2_sleep_mode: spi_sleep {
55*4882a593Smuzhiyun					sleep_cfg1 {
56*4882a593Smuzhiyun						pins =
57*4882a593Smuzhiyun						"GPIO216_AG12", /* FRM */
58*4882a593Smuzhiyun						"GPIO218_AH11"; /* RXD */
59*4882a593Smuzhiyun						ste,config = <&slpm_in_wkup_pdis>;
60*4882a593Smuzhiyun					};
61*4882a593Smuzhiyun					sleep_cfg2 {
62*4882a593Smuzhiyun						pins = "GPIO215_AH13"; /* TXD */
63*4882a593Smuzhiyun						ste,config = <&slpm_out_lo_wkup_pdis>;
64*4882a593Smuzhiyun					};
65*4882a593Smuzhiyun					sleep_cfg3 {
66*4882a593Smuzhiyun						pins = "GPIO217_AH12"; /* CLK */
67*4882a593Smuzhiyun						ste,config = <&slpm_wkup_pdis>;
68*4882a593Smuzhiyun					};
69*4882a593Smuzhiyun				};
70*4882a593Smuzhiyun			};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun			mcde {
73*4882a593Smuzhiyun				lcd_default_mode: lcd_default {
74*4882a593Smuzhiyun					default_mux1 {
75*4882a593Smuzhiyun						/* Mux in VSI0 and all the data lines */
76*4882a593Smuzhiyun						function = "lcd";
77*4882a593Smuzhiyun						groups =
78*4882a593Smuzhiyun						"lcdvsi0_a_1", /* VSI0 for LCD */
79*4882a593Smuzhiyun						"lcd_d0_d7_a_1", /* Data lines */
80*4882a593Smuzhiyun						"lcdvsi1_a_1"; /* VSI1 for HDMI */
81*4882a593Smuzhiyun					};
82*4882a593Smuzhiyun					default_mux2 {
83*4882a593Smuzhiyun						function = "lcda";
84*4882a593Smuzhiyun						groups =
85*4882a593Smuzhiyun						"lcdaclk_b_1"; /* Clock line for TV-out */
86*4882a593Smuzhiyun					};
87*4882a593Smuzhiyun					default_cfg1 {
88*4882a593Smuzhiyun						pins =
89*4882a593Smuzhiyun						"GPIO68_E1", /* VSI0 */
90*4882a593Smuzhiyun						"GPIO69_E2"; /* VSI1 */
91*4882a593Smuzhiyun						ste,config = <&in_pu>;
92*4882a593Smuzhiyun					};
93*4882a593Smuzhiyun				};
94*4882a593Smuzhiyun				lcd_sleep_mode: lcd_sleep {
95*4882a593Smuzhiyun					sleep_cfg1 {
96*4882a593Smuzhiyun						pins = "GPIO69_E2"; /* VSI1 */
97*4882a593Smuzhiyun						ste,config = <&slpm_in_wkup_pdis>;
98*4882a593Smuzhiyun					};
99*4882a593Smuzhiyun				};
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			ske {
103*4882a593Smuzhiyun				/* SKE keys on position 2 in an 8x8 matrix */
104*4882a593Smuzhiyun				ske_kpa2_default_mode: ske_kpa2_default {
105*4882a593Smuzhiyun					default_mux {
106*4882a593Smuzhiyun						function = "kp";
107*4882a593Smuzhiyun						groups = "kp_a_2";
108*4882a593Smuzhiyun					};
109*4882a593Smuzhiyun					default_cfg1 {
110*4882a593Smuzhiyun						pins =
111*4882a593Smuzhiyun						"GPIO153_B17", /* I7 */
112*4882a593Smuzhiyun						"GPIO154_C16", /* I6 */
113*4882a593Smuzhiyun						"GPIO155_C19", /* I5 */
114*4882a593Smuzhiyun						"GPIO156_C17", /* I4 */
115*4882a593Smuzhiyun						"GPIO161_D21", /* I3 */
116*4882a593Smuzhiyun						"GPIO162_D20", /* I2 */
117*4882a593Smuzhiyun						"GPIO163_C20", /* I1 */
118*4882a593Smuzhiyun						"GPIO164_B21"; /* I0 */
119*4882a593Smuzhiyun						ste,config = <&in_pd>;
120*4882a593Smuzhiyun					};
121*4882a593Smuzhiyun					default_cfg2 {
122*4882a593Smuzhiyun						pins =
123*4882a593Smuzhiyun						"GPIO157_A18", /* O7 */
124*4882a593Smuzhiyun						"GPIO158_C18", /* O6 */
125*4882a593Smuzhiyun						"GPIO159_B19", /* O5 */
126*4882a593Smuzhiyun						"GPIO160_B20", /* O4 */
127*4882a593Smuzhiyun						"GPIO165_C21", /* O3 */
128*4882a593Smuzhiyun						"GPIO166_A22", /* O2 */
129*4882a593Smuzhiyun						"GPIO167_B24", /* O1 */
130*4882a593Smuzhiyun						"GPIO168_C22"; /* O0 */
131*4882a593Smuzhiyun						ste,config = <&out_lo>;
132*4882a593Smuzhiyun					};
133*4882a593Smuzhiyun				};
134*4882a593Smuzhiyun				ske_kpa2_sleep_mode: ske_kpa2_sleep {
135*4882a593Smuzhiyun					sleep_cfg1 {
136*4882a593Smuzhiyun						pins =
137*4882a593Smuzhiyun						"GPIO153_B17", /* I7 */
138*4882a593Smuzhiyun						"GPIO154_C16", /* I6 */
139*4882a593Smuzhiyun						"GPIO155_C19", /* I5 */
140*4882a593Smuzhiyun						"GPIO156_C17", /* I4 */
141*4882a593Smuzhiyun						"GPIO161_D21", /* I3 */
142*4882a593Smuzhiyun						"GPIO162_D20", /* I2 */
143*4882a593Smuzhiyun						"GPIO163_C20", /* I1 */
144*4882a593Smuzhiyun						"GPIO164_B21"; /* I0 */
145*4882a593Smuzhiyun						ste,config = <&slpm_in_pu_wkup_pdis_en>;
146*4882a593Smuzhiyun					};
147*4882a593Smuzhiyun					sleep_cfg2 {
148*4882a593Smuzhiyun						pins =
149*4882a593Smuzhiyun						"GPIO157_A18", /* O7 */
150*4882a593Smuzhiyun						"GPIO158_C18", /* O6 */
151*4882a593Smuzhiyun						"GPIO159_B19", /* O5 */
152*4882a593Smuzhiyun						"GPIO160_B20", /* O4 */
153*4882a593Smuzhiyun						"GPIO165_C21", /* O3 */
154*4882a593Smuzhiyun						"GPIO166_A22", /* O2 */
155*4882a593Smuzhiyun						"GPIO167_B24", /* O1 */
156*4882a593Smuzhiyun						"GPIO168_C22"; /* O0 */
157*4882a593Smuzhiyun						ste,config = <&slpm_out_lo_pdis>;
158*4882a593Smuzhiyun					};
159*4882a593Smuzhiyun				};
160*4882a593Smuzhiyun				/*
161*4882a593Smuzhiyun				 * SKE keys on position 1 and "other C1" combi giving
162*4882a593Smuzhiyun				 * six rows of six keys.
163*4882a593Smuzhiyun				 */
164*4882a593Smuzhiyun				ske_kpaoc1_default_mode: ske_kpaoc1_default {
165*4882a593Smuzhiyun					default_mux {
166*4882a593Smuzhiyun						function = "kp";
167*4882a593Smuzhiyun						groups = "kp_a_1", "kp_oc1_1";
168*4882a593Smuzhiyun					};
169*4882a593Smuzhiyun					default_cfg1 {
170*4882a593Smuzhiyun						pins =
171*4882a593Smuzhiyun						"GPIO91_B6", /* KP_O0 */
172*4882a593Smuzhiyun						"GPIO90_A3", /* KP_O1 */
173*4882a593Smuzhiyun						"GPIO87_B3", /* KP_O2 */
174*4882a593Smuzhiyun						"GPIO86_C6", /* KP_O3 */
175*4882a593Smuzhiyun						"GPIO96_D8", /* KP_O6 */
176*4882a593Smuzhiyun						"GPIO94_D7"; /* KP_O7 */
177*4882a593Smuzhiyun						ste,config = <&out_lo>;
178*4882a593Smuzhiyun					};
179*4882a593Smuzhiyun					default_cfg2 {
180*4882a593Smuzhiyun						pins =
181*4882a593Smuzhiyun						"GPIO93_B7", /* KP_I0 */
182*4882a593Smuzhiyun						"GPIO92_D6", /* KP_I1 */
183*4882a593Smuzhiyun						"GPIO89_E6", /* KP_I2 */
184*4882a593Smuzhiyun						"GPIO88_C4", /* KP_I3 */
185*4882a593Smuzhiyun						"GPIO97_D9", /* KP_I6 */
186*4882a593Smuzhiyun						"GPIO95_E8"; /* KP_I7 */
187*4882a593Smuzhiyun						ste,config = <&in_pu>;
188*4882a593Smuzhiyun					};
189*4882a593Smuzhiyun				};
190*4882a593Smuzhiyun			};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun			wlan {
193*4882a593Smuzhiyun				wlan_default_mode: wlan_default {
194*4882a593Smuzhiyun					/*
195*4882a593Smuzhiyun					 * Activate this mode with the WLAN chip.
196*4882a593Smuzhiyun					 * These are plain GPIO pins used by WLAN
197*4882a593Smuzhiyun					 */
198*4882a593Smuzhiyun					default_cfg1 {
199*4882a593Smuzhiyun						pins =
200*4882a593Smuzhiyun						"GPIO226_AF8", /* WLAN_PMU_EN */
201*4882a593Smuzhiyun						"GPIO85_D5"; /* WLAN_ENA */
202*4882a593Smuzhiyun						ste,config = <&gpio_out_lo>;
203*4882a593Smuzhiyun					};
204*4882a593Smuzhiyun					default_cfg2 {
205*4882a593Smuzhiyun						pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
206*4882a593Smuzhiyun						ste,config = <&gpio_in_pu>;
207*4882a593Smuzhiyun					};
208*4882a593Smuzhiyun				};
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun};
213