1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2014 Linaro Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "ste-ab8500.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun soc { 10*4882a593Smuzhiyun prcmu@80157000 { 11*4882a593Smuzhiyun ab8500 { 12*4882a593Smuzhiyun ab8500-gpiocontroller { 13*4882a593Smuzhiyun /* Hog a few default settings */ 14*4882a593Smuzhiyun pinctrl-names = "default"; 15*4882a593Smuzhiyun pinctrl-0 = <&gpio2_default_mode>, 16*4882a593Smuzhiyun <&gpio4_default_mode>, 17*4882a593Smuzhiyun <&gpio10_default_mode>, 18*4882a593Smuzhiyun <&gpio11_default_mode>, 19*4882a593Smuzhiyun <&gpio12_default_mode>, 20*4882a593Smuzhiyun <&gpio13_default_mode>, 21*4882a593Smuzhiyun <&gpio16_default_mode>, 22*4882a593Smuzhiyun <&gpio24_default_mode>, 23*4882a593Smuzhiyun <&gpio25_default_mode>, 24*4882a593Smuzhiyun <&gpio36_default_mode>, 25*4882a593Smuzhiyun <&gpio37_default_mode>, 26*4882a593Smuzhiyun <&gpio38_default_mode>, 27*4882a593Smuzhiyun <&gpio39_default_mode>, 28*4882a593Smuzhiyun <&gpio42_default_mode>, 29*4882a593Smuzhiyun <&gpio26_default_mode>, 30*4882a593Smuzhiyun <&gpio35_default_mode>, 31*4882a593Smuzhiyun <&ycbcr_default_mode>, 32*4882a593Smuzhiyun <&pwm_default_mode>, 33*4882a593Smuzhiyun <&adi1_default_mode>, 34*4882a593Smuzhiyun <&usbuicc_default_mode>, 35*4882a593Smuzhiyun <&dmic_default_mode>, 36*4882a593Smuzhiyun <&extcpena_default_mode>, 37*4882a593Smuzhiyun <&modsclsda_default_mode>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 41*4882a593Smuzhiyun * are muxed in as GPIO, and configured as INPUT PULL DOWN 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun gpio2 { 44*4882a593Smuzhiyun gpio2_default_mode: gpio2_default { 45*4882a593Smuzhiyun default_mux { 46*4882a593Smuzhiyun function = "gpio"; 47*4882a593Smuzhiyun groups = "gpio2_a_1"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun default_cfg { 50*4882a593Smuzhiyun pins = "GPIO2_T9"; 51*4882a593Smuzhiyun input-enable; 52*4882a593Smuzhiyun bias-pull-down; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun gpio4 { 57*4882a593Smuzhiyun gpio4_default_mode: gpio4_default { 58*4882a593Smuzhiyun default_mux { 59*4882a593Smuzhiyun function = "gpio"; 60*4882a593Smuzhiyun groups = "gpio4_a_1"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun default_cfg { 63*4882a593Smuzhiyun pins = "GPIO4_W2"; 64*4882a593Smuzhiyun input-enable; 65*4882a593Smuzhiyun bias-pull-down; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun gpio10 { 70*4882a593Smuzhiyun gpio10_default_mode: gpio10_default { 71*4882a593Smuzhiyun default_mux { 72*4882a593Smuzhiyun function = "gpio"; 73*4882a593Smuzhiyun groups = "gpio10_d_1"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun default_cfg { 76*4882a593Smuzhiyun pins = "GPIO10_U17"; 77*4882a593Smuzhiyun input-enable; 78*4882a593Smuzhiyun bias-pull-down; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun gpio11 { 83*4882a593Smuzhiyun gpio11_default_mode: gpio11_default { 84*4882a593Smuzhiyun default_mux { 85*4882a593Smuzhiyun function = "gpio"; 86*4882a593Smuzhiyun groups = "gpio11_d_1"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun default_cfg { 89*4882a593Smuzhiyun pins = "GPIO11_AA18"; 90*4882a593Smuzhiyun input-enable; 91*4882a593Smuzhiyun bias-pull-down; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun gpio12 { 96*4882a593Smuzhiyun gpio12_default_mode: gpio12_default { 97*4882a593Smuzhiyun default_mux { 98*4882a593Smuzhiyun function = "gpio"; 99*4882a593Smuzhiyun groups = "gpio12_d_1"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun default_cfg { 102*4882a593Smuzhiyun pins = "GPIO12_U16"; 103*4882a593Smuzhiyun input-enable; 104*4882a593Smuzhiyun bias-pull-down; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun gpio13 { 109*4882a593Smuzhiyun gpio13_default_mode: gpio13_default { 110*4882a593Smuzhiyun default_mux { 111*4882a593Smuzhiyun function = "gpio"; 112*4882a593Smuzhiyun groups = "gpio13_d_1"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun default_cfg { 115*4882a593Smuzhiyun pins = "GPIO13_W17"; 116*4882a593Smuzhiyun input-enable; 117*4882a593Smuzhiyun bias-pull-down; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun gpio16 { 122*4882a593Smuzhiyun gpio16_default_mode: gpio16_default { 123*4882a593Smuzhiyun default_mux { 124*4882a593Smuzhiyun function = "gpio"; 125*4882a593Smuzhiyun groups = "gpio16_a_1"; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun default_cfg { 128*4882a593Smuzhiyun pins = "GPIO16_F15"; 129*4882a593Smuzhiyun input-enable; 130*4882a593Smuzhiyun bias-pull-down; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun gpio24 { 135*4882a593Smuzhiyun gpio24_default_mode: gpio24_default { 136*4882a593Smuzhiyun default_mux { 137*4882a593Smuzhiyun function = "gpio"; 138*4882a593Smuzhiyun groups = "gpio24_a_1"; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun default_cfg { 141*4882a593Smuzhiyun pins = "GPIO24_T14"; 142*4882a593Smuzhiyun input-enable; 143*4882a593Smuzhiyun bias-pull-down; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun gpio25 { 148*4882a593Smuzhiyun gpio25_default_mode: gpio25_default { 149*4882a593Smuzhiyun default_mux { 150*4882a593Smuzhiyun function = "gpio"; 151*4882a593Smuzhiyun groups = "gpio25_a_1"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun default_cfg { 154*4882a593Smuzhiyun pins = "GPIO25_R16"; 155*4882a593Smuzhiyun input-enable; 156*4882a593Smuzhiyun bias-pull-down; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun gpio36 { 161*4882a593Smuzhiyun gpio36_default_mode: gpio36_default { 162*4882a593Smuzhiyun default_mux { 163*4882a593Smuzhiyun function = "gpio"; 164*4882a593Smuzhiyun groups = "gpio36_a_1"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun default_cfg { 167*4882a593Smuzhiyun pins = "GPIO36_A17"; 168*4882a593Smuzhiyun input-enable; 169*4882a593Smuzhiyun bias-pull-down; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun gpio37 { 174*4882a593Smuzhiyun gpio37_default_mode: gpio37_default { 175*4882a593Smuzhiyun default_mux { 176*4882a593Smuzhiyun function = "gpio"; 177*4882a593Smuzhiyun groups = "gpio37_a_1"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun default_cfg { 180*4882a593Smuzhiyun pins = "GPIO37_E15"; 181*4882a593Smuzhiyun input-enable; 182*4882a593Smuzhiyun bias-pull-down; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun gpio38 { 187*4882a593Smuzhiyun gpio38_default_mode: gpio38_default { 188*4882a593Smuzhiyun default_mux { 189*4882a593Smuzhiyun function = "gpio"; 190*4882a593Smuzhiyun groups = "gpio38_a_1"; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun default_cfg { 193*4882a593Smuzhiyun pins = "GPIO38_C17"; 194*4882a593Smuzhiyun input-enable; 195*4882a593Smuzhiyun bias-pull-down; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun gpio39 { 200*4882a593Smuzhiyun gpio39_default_mode: gpio39_default { 201*4882a593Smuzhiyun default_mux { 202*4882a593Smuzhiyun function = "gpio"; 203*4882a593Smuzhiyun groups = "gpio39_a_1"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun default_cfg { 206*4882a593Smuzhiyun pins = "GPIO39_E16"; 207*4882a593Smuzhiyun input-enable; 208*4882a593Smuzhiyun bias-pull-down; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun gpio42 { 213*4882a593Smuzhiyun gpio42_default_mode: gpio42_default { 214*4882a593Smuzhiyun default_mux { 215*4882a593Smuzhiyun function = "gpio"; 216*4882a593Smuzhiyun groups = "gpio42_a_1"; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun default_cfg { 219*4882a593Smuzhiyun pins = "GPIO42_U2"; 220*4882a593Smuzhiyun input-enable; 221*4882a593Smuzhiyun bias-pull-down; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun /* 226*4882a593Smuzhiyun * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW 227*4882a593Smuzhiyun */ 228*4882a593Smuzhiyun gpio26 { 229*4882a593Smuzhiyun gpio26_default_mode: gpio26_default { 230*4882a593Smuzhiyun default_mux { 231*4882a593Smuzhiyun function = "gpio"; 232*4882a593Smuzhiyun groups = "gpio26_d_1"; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun default_cfg { 235*4882a593Smuzhiyun pins = "GPIO26_M16"; 236*4882a593Smuzhiyun output-low; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun gpio35 { 241*4882a593Smuzhiyun gpio35_default_mode: gpio35_default { 242*4882a593Smuzhiyun default_mux { 243*4882a593Smuzhiyun function = "gpio"; 244*4882a593Smuzhiyun groups = "gpio35_d_1"; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun default_cfg { 247*4882a593Smuzhiyun pins = "GPIO35_W15"; 248*4882a593Smuzhiyun output-low; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun /* 253*4882a593Smuzhiyun * This sets up the YCBCR connector pins, i.e. analog video out. 254*4882a593Smuzhiyun * Set as input with no bias. 255*4882a593Smuzhiyun */ 256*4882a593Smuzhiyun ycbcr { 257*4882a593Smuzhiyun ycbcr_default_mode: ycbcr_default { 258*4882a593Smuzhiyun default_mux { 259*4882a593Smuzhiyun function = "ycbcr"; 260*4882a593Smuzhiyun groups = "ycbcr0123_d_1"; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun default_cfg { 263*4882a593Smuzhiyun pins = "GPIO6_Y18", 264*4882a593Smuzhiyun "GPIO7_AA20", 265*4882a593Smuzhiyun "GPIO8_W18", 266*4882a593Smuzhiyun "GPIO9_AA19"; 267*4882a593Smuzhiyun input-enable; 268*4882a593Smuzhiyun bias-disable; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun /* This sets up the PWM pins 14 and 15 */ 273*4882a593Smuzhiyun pwm { 274*4882a593Smuzhiyun pwm_default_mode: pwm_default { 275*4882a593Smuzhiyun default_mux { 276*4882a593Smuzhiyun function = "pwmout"; 277*4882a593Smuzhiyun groups = "pwmout1_d_1", "pwmout2_d_1"; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun default_cfg { 280*4882a593Smuzhiyun pins = "GPIO14_F14", 281*4882a593Smuzhiyun "GPIO15_B17"; 282*4882a593Smuzhiyun input-enable; 283*4882a593Smuzhiyun bias-pull-down; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun /* This sets up audio interface 1 */ 288*4882a593Smuzhiyun adi1 { 289*4882a593Smuzhiyun adi1_default_mode: adi1_default { 290*4882a593Smuzhiyun default_mux { 291*4882a593Smuzhiyun function = "adi1"; 292*4882a593Smuzhiyun groups = "adi1_d_1"; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun default_cfg { 295*4882a593Smuzhiyun pins = "GPIO17_P5", 296*4882a593Smuzhiyun "GPIO18_R5", 297*4882a593Smuzhiyun "GPIO19_U5", 298*4882a593Smuzhiyun "GPIO20_T5"; 299*4882a593Smuzhiyun input-enable; 300*4882a593Smuzhiyun bias-pull-down; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun /* This sets up the USB UICC pins */ 305*4882a593Smuzhiyun usbuicc { 306*4882a593Smuzhiyun usbuicc_default_mode: usbuicc_default { 307*4882a593Smuzhiyun default_mux { 308*4882a593Smuzhiyun function = "usbuicc"; 309*4882a593Smuzhiyun groups = "usbuicc_d_1"; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun default_cfg { 312*4882a593Smuzhiyun pins = "GPIO21_H19", 313*4882a593Smuzhiyun "GPIO22_G20", 314*4882a593Smuzhiyun "GPIO23_G19"; 315*4882a593Smuzhiyun input-enable; 316*4882a593Smuzhiyun bias-pull-down; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun /* This sets up the microphone pins */ 321*4882a593Smuzhiyun dmic { 322*4882a593Smuzhiyun dmic_default_mode: dmic_default { 323*4882a593Smuzhiyun default_mux { 324*4882a593Smuzhiyun function = "dmic"; 325*4882a593Smuzhiyun groups = "dmic12_d_1", 326*4882a593Smuzhiyun "dmic34_d_1", 327*4882a593Smuzhiyun "dmic56_d_1"; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun default_cfg { 330*4882a593Smuzhiyun pins = "GPIO27_J6", 331*4882a593Smuzhiyun "GPIO28_K6", 332*4882a593Smuzhiyun "GPIO29_G6", 333*4882a593Smuzhiyun "GPIO30_H6", 334*4882a593Smuzhiyun "GPIO31_F5", 335*4882a593Smuzhiyun "GPIO32_G5"; 336*4882a593Smuzhiyun input-enable; 337*4882a593Smuzhiyun bias-pull-down; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun extcpena { 342*4882a593Smuzhiyun extcpena_default_mode: extcpena_default { 343*4882a593Smuzhiyun default_mux { 344*4882a593Smuzhiyun function = "extcpena"; 345*4882a593Smuzhiyun groups = "extcpena_d_1"; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun default_cfg { 348*4882a593Smuzhiyun pins = "GPIO34_R17"; 349*4882a593Smuzhiyun input-enable; 350*4882a593Smuzhiyun bias-pull-down; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun /* Modem I2C setup (SCL and SDA pins) */ 355*4882a593Smuzhiyun modsclsda { 356*4882a593Smuzhiyun modsclsda_default_mode: modsclsda_default { 357*4882a593Smuzhiyun default_mux { 358*4882a593Smuzhiyun function = "modsclsda"; 359*4882a593Smuzhiyun groups = "modsclsda_d_1"; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun default_cfg { 362*4882a593Smuzhiyun pins = "GPIO40_T19", 363*4882a593Smuzhiyun "GPIO41_U19"; 364*4882a593Smuzhiyun input-enable; 365*4882a593Smuzhiyun bias-pull-down; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun /* 370*4882a593Smuzhiyun * Clock output pins associated with regulators. 371*4882a593Smuzhiyun */ 372*4882a593Smuzhiyun sysclkreq2 { 373*4882a593Smuzhiyun sysclkreq2_default_mode: sysclkreq2_default { 374*4882a593Smuzhiyun default_mux { 375*4882a593Smuzhiyun function = "sysclkreq"; 376*4882a593Smuzhiyun groups = "sysclkreq2_d_1"; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun default_cfg { 379*4882a593Smuzhiyun pins = "GPIO1_T10"; 380*4882a593Smuzhiyun input-enable; 381*4882a593Smuzhiyun bias-disable; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun sysclkreq2_sleep_mode: sysclkreq2_sleep { 385*4882a593Smuzhiyun default_mux { 386*4882a593Smuzhiyun function = "gpio"; 387*4882a593Smuzhiyun groups = "gpio1_a_1"; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun default_cfg { 390*4882a593Smuzhiyun pins = "GPIO1_T10"; 391*4882a593Smuzhiyun input-enable; 392*4882a593Smuzhiyun bias-pull-down; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun sysclkreq4 { 397*4882a593Smuzhiyun sysclkreq4_default_mode: sysclkreq4_default { 398*4882a593Smuzhiyun default_mux { 399*4882a593Smuzhiyun function = "sysclkreq"; 400*4882a593Smuzhiyun groups = "sysclkreq4_d_1"; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun default_cfg { 403*4882a593Smuzhiyun pins = "GPIO3_U9"; 404*4882a593Smuzhiyun input-enable; 405*4882a593Smuzhiyun bias-disable; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun sysclkreq4_sleep_mode: sysclkreq4_sleep { 409*4882a593Smuzhiyun default_mux { 410*4882a593Smuzhiyun function = "gpio"; 411*4882a593Smuzhiyun groups = "gpio3_a_1"; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun default_cfg { 414*4882a593Smuzhiyun pins = "GPIO3_U9"; 415*4882a593Smuzhiyun input-enable; 416*4882a593Smuzhiyun bias-pull-down; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun}; 425