1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for all SPEAr1340 SoCs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "spear13xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "st,spear1340"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun ahb { 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun spics: spics@e0700000{ 16*4882a593Smuzhiyun compatible = "st,spear-spics-gpio"; 17*4882a593Smuzhiyun reg = <0xe0700000 0x1000>; 18*4882a593Smuzhiyun st-spics,peripcfg-reg = <0x42c>; 19*4882a593Smuzhiyun st-spics,sw-enable-bit = <21>; 20*4882a593Smuzhiyun st-spics,cs-value-bit = <20>; 21*4882a593Smuzhiyun st-spics,cs-enable-mask = <3>; 22*4882a593Smuzhiyun st-spics,cs-enable-shift = <18>; 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun #gpio-cells = <2>; 25*4882a593Smuzhiyun status = "disabled"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun miphy0: miphy@eb800000 { 29*4882a593Smuzhiyun compatible = "st,spear1340-miphy"; 30*4882a593Smuzhiyun reg = <0xeb800000 0x4000>; 31*4882a593Smuzhiyun misc = <&misc>; 32*4882a593Smuzhiyun #phy-cells = <1>; 33*4882a593Smuzhiyun status = "disabled"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ahci0: ahci@b1000000 { 37*4882a593Smuzhiyun compatible = "snps,spear-ahci"; 38*4882a593Smuzhiyun reg = <0xb1000000 0x10000>; 39*4882a593Smuzhiyun interrupts = <0 72 0x4>; 40*4882a593Smuzhiyun phys = <&miphy0 0>; 41*4882a593Smuzhiyun phy-names = "sata-phy"; 42*4882a593Smuzhiyun status = "disabled"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pcie0: pcie@b1000000 { 46*4882a593Smuzhiyun compatible = "st,spear1340-pcie", "snps,dw-pcie"; 47*4882a593Smuzhiyun reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; 48*4882a593Smuzhiyun reg-names = "dbi", "config"; 49*4882a593Smuzhiyun interrupts = <0 68 0x4>; 50*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 51*4882a593Smuzhiyun interrupt-map = <0x0 0 &gic 0 68 0x4>; 52*4882a593Smuzhiyun num-lanes = <1>; 53*4882a593Smuzhiyun phys = <&miphy0 1>; 54*4882a593Smuzhiyun phy-names = "pcie-phy"; 55*4882a593Smuzhiyun #address-cells = <3>; 56*4882a593Smuzhiyun #size-cells = <2>; 57*4882a593Smuzhiyun device_type = "pci"; 58*4882a593Smuzhiyun ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 59*4882a593Smuzhiyun 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 60*4882a593Smuzhiyun bus-range = <0x00 0xff>; 61*4882a593Smuzhiyun status = "disabled"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun i2s-play@b2400000 { 65*4882a593Smuzhiyun compatible = "snps,designware-i2s"; 66*4882a593Smuzhiyun reg = <0xb2400000 0x10000>; 67*4882a593Smuzhiyun interrupt-names = "play_irq"; 68*4882a593Smuzhiyun interrupts = <0 98 0x4 69*4882a593Smuzhiyun 0 99 0x4>; 70*4882a593Smuzhiyun play; 71*4882a593Smuzhiyun channel = <8>; 72*4882a593Smuzhiyun status = "disabled"; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun i2s-rec@b2000000 { 76*4882a593Smuzhiyun compatible = "snps,designware-i2s"; 77*4882a593Smuzhiyun reg = <0xb2000000 0x10000>; 78*4882a593Smuzhiyun interrupt-names = "record_irq"; 79*4882a593Smuzhiyun interrupts = <0 100 0x4 80*4882a593Smuzhiyun 0 101 0x4>; 81*4882a593Smuzhiyun record; 82*4882a593Smuzhiyun channel = <8>; 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pinmux: pinmux@e0700000 { 87*4882a593Smuzhiyun compatible = "st,spear1340-pinmux"; 88*4882a593Smuzhiyun reg = <0xe0700000 0x1000>; 89*4882a593Smuzhiyun #gpio-range-cells = <3>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun pwm: pwm@e0180000 { 93*4882a593Smuzhiyun compatible ="st,spear13xx-pwm"; 94*4882a593Smuzhiyun reg = <0xe0180000 0x1000>; 95*4882a593Smuzhiyun #pwm-cells = <2>; 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun spdif-in@d0100000 { 100*4882a593Smuzhiyun compatible = "st,spdif-in"; 101*4882a593Smuzhiyun reg = < 0xd0100000 0x20000 102*4882a593Smuzhiyun 0xd0110000 0x10000 >; 103*4882a593Smuzhiyun interrupts = <0 84 0x4>; 104*4882a593Smuzhiyun status = "disabled"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun spdif-out@d0000000 { 108*4882a593Smuzhiyun compatible = "st,spdif-out"; 109*4882a593Smuzhiyun reg = <0xd0000000 0x20000>; 110*4882a593Smuzhiyun interrupts = <0 85 0x4>; 111*4882a593Smuzhiyun status = "disabled"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun spi1: spi@5d400000 { 115*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 116*4882a593Smuzhiyun reg = <0x5d400000 0x1000>; 117*4882a593Smuzhiyun #address-cells = <1>; 118*4882a593Smuzhiyun #size-cells = <0>; 119*4882a593Smuzhiyun interrupts = <0 99 0x4>; 120*4882a593Smuzhiyun status = "disabled"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun apb { 124*4882a593Smuzhiyun i2c1: i2c@b4000000 { 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun #size-cells = <0>; 127*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 128*4882a593Smuzhiyun reg = <0xb4000000 0x1000>; 129*4882a593Smuzhiyun interrupts = <0 104 0x4>; 130*4882a593Smuzhiyun write-16bit; 131*4882a593Smuzhiyun status = "disabled"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun serial@b4100000 { 135*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 136*4882a593Smuzhiyun reg = <0xb4100000 0x1000>; 137*4882a593Smuzhiyun interrupts = <0 105 0x4>; 138*4882a593Smuzhiyun status = "disabled"; 139*4882a593Smuzhiyun dmas = <&dwdma0 13 0 1>, 140*4882a593Smuzhiyun <&dwdma0 12 1 0>; 141*4882a593Smuzhiyun dma-names = "rx", "tx"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun thermal@e07008c4 { 145*4882a593Smuzhiyun st,thermal-flags = <0x2a00>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun gpiopinctrl: gpio@e2800000 { 149*4882a593Smuzhiyun compatible = "st,spear-plgpio"; 150*4882a593Smuzhiyun reg = <0xe2800000 0x1000>; 151*4882a593Smuzhiyun interrupts = <0 107 0x4>; 152*4882a593Smuzhiyun #interrupt-cells = <1>; 153*4882a593Smuzhiyun interrupt-controller; 154*4882a593Smuzhiyun gpio-controller; 155*4882a593Smuzhiyun #gpio-cells = <2>; 156*4882a593Smuzhiyun gpio-ranges = <&pinmux 0 0 252>; 157*4882a593Smuzhiyun status = "disabled"; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun st-plgpio,ngpio = <250>; 160*4882a593Smuzhiyun st-plgpio,wdata-reg = <0x40>; 161*4882a593Smuzhiyun st-plgpio,dir-reg = <0x00>; 162*4882a593Smuzhiyun st-plgpio,ie-reg = <0x80>; 163*4882a593Smuzhiyun st-plgpio,rdata-reg = <0x20>; 164*4882a593Smuzhiyun st-plgpio,mis-reg = <0xa0>; 165*4882a593Smuzhiyun st-plgpio,eit-reg = <0x60>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun}; 170