1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Altera Corporation <www.altera.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "socfpga_cyclone5.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Altera SOCFPGA Cyclone V SoC Development Kit"; 10*4882a593Smuzhiyun compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun chosen { 13*4882a593Smuzhiyun bootargs = "earlyprintk"; 14*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@0 { 18*4882a593Smuzhiyun name = "memory"; 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x0 0x40000000>; /* 1GB */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun aliases { 24*4882a593Smuzhiyun /* this allow the ethaddr uboot environmnet variable contents 25*4882a593Smuzhiyun * to be added to the gmac1 device tree blob. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun ethernet0 = &gmac1; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun leds { 31*4882a593Smuzhiyun compatible = "gpio-leds"; 32*4882a593Smuzhiyun hps0 { 33*4882a593Smuzhiyun label = "hps_led0"; 34*4882a593Smuzhiyun gpios = <&portb 15 1>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun hps1 { 38*4882a593Smuzhiyun label = "hps_led1"; 39*4882a593Smuzhiyun gpios = <&portb 14 1>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun hps2 { 43*4882a593Smuzhiyun label = "hps_led2"; 44*4882a593Smuzhiyun gpios = <&portb 13 1>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun hps3 { 48*4882a593Smuzhiyun label = "hps_led3"; 49*4882a593Smuzhiyun gpios = <&portb 12 1>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun regulator_3_3v: 3-3-v-regulator { 54*4882a593Smuzhiyun compatible = "regulator-fixed"; 55*4882a593Smuzhiyun regulator-name = "3.3V"; 56*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 57*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&can0 { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&gmac1 { 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun phy-mode = "rgmii"; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun rxd0-skew-ps = <0>; 70*4882a593Smuzhiyun rxd1-skew-ps = <0>; 71*4882a593Smuzhiyun rxd2-skew-ps = <0>; 72*4882a593Smuzhiyun rxd3-skew-ps = <0>; 73*4882a593Smuzhiyun txen-skew-ps = <0>; 74*4882a593Smuzhiyun txc-skew-ps = <2600>; 75*4882a593Smuzhiyun rxdv-skew-ps = <0>; 76*4882a593Smuzhiyun rxc-skew-ps = <2000>; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&gpio0 { 80*4882a593Smuzhiyun status = "okay"; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&gpio1 { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&gpio2 { 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&i2c0 { 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun clock-frequency = <100000>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * adjust the falling times to decrease the i2c frequency to 50Khz 97*4882a593Smuzhiyun * because the LCD module does not work at the standard 100Khz 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun i2c-sda-falling-time-ns = <5000>; 100*4882a593Smuzhiyun i2c-scl-falling-time-ns = <5000>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun eeprom@51 { 103*4882a593Smuzhiyun compatible = "atmel,24c32"; 104*4882a593Smuzhiyun reg = <0x51>; 105*4882a593Smuzhiyun pagesize = <32>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun rtc@68 { 109*4882a593Smuzhiyun compatible = "dallas,ds1339"; 110*4882a593Smuzhiyun reg = <0x68>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&mmc0 { 115*4882a593Smuzhiyun cd-gpios = <&portb 18 0>; 116*4882a593Smuzhiyun vmmc-supply = <®ulator_3_3v>; 117*4882a593Smuzhiyun vqmmc-supply = <®ulator_3_3v>; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&qspi { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun flash0: n25q00@0 { 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun #size-cells = <1>; 127*4882a593Smuzhiyun compatible = "micron,mt25qu02g", "jedec,spi-nor"; 128*4882a593Smuzhiyun reg = <0>; /* chip select */ 129*4882a593Smuzhiyun spi-max-frequency = <100000000>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun m25p,fast-read; 132*4882a593Smuzhiyun cdns,page-size = <256>; 133*4882a593Smuzhiyun cdns,block-size = <16>; 134*4882a593Smuzhiyun cdns,read-delay = <4>; 135*4882a593Smuzhiyun cdns,tshsl-ns = <50>; 136*4882a593Smuzhiyun cdns,tsd2d-ns = <50>; 137*4882a593Smuzhiyun cdns,tchsh-ns = <4>; 138*4882a593Smuzhiyun cdns,tslch-ns = <4>; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun partition@qspi-boot { 141*4882a593Smuzhiyun /* 8MB for raw data. */ 142*4882a593Smuzhiyun label = "Flash 0 Raw Data"; 143*4882a593Smuzhiyun reg = <0x0 0x800000>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun partition@qspi-rootfs { 147*4882a593Smuzhiyun /* 120MB for jffs2 data. */ 148*4882a593Smuzhiyun label = "Flash 0 jffs2 Filesystem"; 149*4882a593Smuzhiyun reg = <0x800000 0x7800000>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&spi0 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun spidev@0 { 158*4882a593Smuzhiyun compatible = "rohm,dh2228fv"; 159*4882a593Smuzhiyun reg = <0>; 160*4882a593Smuzhiyun spi-max-frequency = <1000000>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&usb1 { 165*4882a593Smuzhiyun status = "okay"; 166*4882a593Smuzhiyun}; 167