1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Hisilicon Limited. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * DTS file for Hisilicon SD5203 Board 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Hisilicon SD5203"; 12*4882a593Smuzhiyun compatible = "H836ASDJ", "hisilicon,sd5203"; 13*4882a593Smuzhiyun interrupt-parent = <&vic>; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun aliases { 22*4882a593Smuzhiyun serial0 = &uart0; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpus { 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun cpu0 { 30*4882a593Smuzhiyun device_type = "cpu"; 31*4882a593Smuzhiyun compatible = "arm,arm926ej-s"; 32*4882a593Smuzhiyun reg = <0x0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun memory@30000000 { 37*4882a593Smuzhiyun device_type = "memory"; 38*4882a593Smuzhiyun reg = <0x30000000 0x8000000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun soc { 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <1>; 44*4882a593Smuzhiyun compatible = "simple-bus"; 45*4882a593Smuzhiyun ranges; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vic: interrupt-controller@10130000 { 48*4882a593Smuzhiyun compatible = "snps,dw-apb-ictl"; 49*4882a593Smuzhiyun reg = <0x10130000 0x1000>; 50*4882a593Smuzhiyun interrupt-controller; 51*4882a593Smuzhiyun #interrupt-cells = <1>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun refclk125mhz: refclk125mhz { 55*4882a593Smuzhiyun compatible = "fixed-clock"; 56*4882a593Smuzhiyun #clock-cells = <0>; 57*4882a593Smuzhiyun clock-frequency = <125000000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun timer0: timer@16002000 { 61*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 62*4882a593Smuzhiyun reg = <0x16002000 0x1000>; 63*4882a593Smuzhiyun interrupts = <4>; 64*4882a593Smuzhiyun clocks = <&refclk125mhz>; 65*4882a593Smuzhiyun clock-names = "apb_pclk"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun timer1: timer@16003000 { 69*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 70*4882a593Smuzhiyun reg = <0x16003000 0x1000>; 71*4882a593Smuzhiyun interrupts = <5>; 72*4882a593Smuzhiyun clocks = <&refclk125mhz>; 73*4882a593Smuzhiyun clock-names = "apb_pclk"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun uart0: serial@1600d000 { 77*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 78*4882a593Smuzhiyun reg = <0x1600d000 0x1000>; 79*4882a593Smuzhiyun bus_id = "uart0"; 80*4882a593Smuzhiyun clocks = <&refclk125mhz>; 81*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 82*4882a593Smuzhiyun reg-shift = <2>; 83*4882a593Smuzhiyun interrupts = <17>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun uart1: serial@1600c000 { 87*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 88*4882a593Smuzhiyun reg = <0x1600c000 0x1000>; 89*4882a593Smuzhiyun clocks = <&refclk125mhz>; 90*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 91*4882a593Smuzhiyun reg-shift = <2>; 92*4882a593Smuzhiyun interrupts = <16>; 93*4882a593Smuzhiyun status = "disabled"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun}; 97