xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/s3c64xx.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Samsung's S3C64xx SoC series common device tree source
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Samsung's S3C64xx SoC series device nodes are listed in this file.
8*4882a593Smuzhiyun * Particular SoCs from S3C64xx series can include this file and provide
9*4882a593Smuzhiyun * values for SoCs specfic bindings.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Note: This file does not include device nodes for all the controllers in
12*4882a593Smuzhiyun * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
13*4882a593Smuzhiyun * nodes can be added to this file.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun/ {
19*4882a593Smuzhiyun	#address-cells = <1>;
20*4882a593Smuzhiyun	#size-cells = <1>;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	aliases {
23*4882a593Smuzhiyun		i2c0 = &i2c0;
24*4882a593Smuzhiyun		pinctrl0 = &pinctrl0;
25*4882a593Smuzhiyun		serial0 = &uart0;
26*4882a593Smuzhiyun		serial1 = &uart1;
27*4882a593Smuzhiyun		serial2 = &uart2;
28*4882a593Smuzhiyun		serial3 = &uart3;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	cpus {
32*4882a593Smuzhiyun		#address-cells = <1>;
33*4882a593Smuzhiyun		#size-cells = <0>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		cpu@0 {
36*4882a593Smuzhiyun			device_type = "cpu";
37*4882a593Smuzhiyun			compatible = "arm,arm1176jzf-s";
38*4882a593Smuzhiyun			reg = <0x0>;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	soc: soc {
43*4882a593Smuzhiyun		compatible = "simple-bus";
44*4882a593Smuzhiyun		#address-cells = <1>;
45*4882a593Smuzhiyun		#size-cells = <1>;
46*4882a593Smuzhiyun		ranges;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun		vic0: interrupt-controller@71200000 {
49*4882a593Smuzhiyun			compatible = "arm,pl192-vic";
50*4882a593Smuzhiyun			interrupt-controller;
51*4882a593Smuzhiyun			reg = <0x71200000 0x1000>;
52*4882a593Smuzhiyun			#interrupt-cells = <1>;
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		vic1: interrupt-controller@71300000 {
56*4882a593Smuzhiyun			compatible = "arm,pl192-vic";
57*4882a593Smuzhiyun			interrupt-controller;
58*4882a593Smuzhiyun			reg = <0x71300000 0x1000>;
59*4882a593Smuzhiyun			#interrupt-cells = <1>;
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		sdhci0: sdhci@7c200000 {
63*4882a593Smuzhiyun			compatible = "samsung,s3c6410-sdhci";
64*4882a593Smuzhiyun			reg = <0x7c200000 0x100>;
65*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
66*4882a593Smuzhiyun			interrupts = <24>;
67*4882a593Smuzhiyun			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
68*4882a593Smuzhiyun			clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69*4882a593Smuzhiyun					<&clocks SCLK_MMC0>;
70*4882a593Smuzhiyun			status = "disabled";
71*4882a593Smuzhiyun		};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun		sdhci1: sdhci@7c300000 {
74*4882a593Smuzhiyun			compatible = "samsung,s3c6410-sdhci";
75*4882a593Smuzhiyun			reg = <0x7c300000 0x100>;
76*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
77*4882a593Smuzhiyun			interrupts = <25>;
78*4882a593Smuzhiyun			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
79*4882a593Smuzhiyun			clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80*4882a593Smuzhiyun					<&clocks SCLK_MMC1>;
81*4882a593Smuzhiyun			status = "disabled";
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		sdhci2: sdhci@7c400000 {
85*4882a593Smuzhiyun			compatible = "samsung,s3c6410-sdhci";
86*4882a593Smuzhiyun			reg = <0x7c400000 0x100>;
87*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
88*4882a593Smuzhiyun			interrupts = <17>;
89*4882a593Smuzhiyun			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
90*4882a593Smuzhiyun			clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91*4882a593Smuzhiyun					<&clocks SCLK_MMC2>;
92*4882a593Smuzhiyun			status = "disabled";
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		watchdog: watchdog@7e004000 {
96*4882a593Smuzhiyun			compatible = "samsung,s3c6410-wdt";
97*4882a593Smuzhiyun			reg = <0x7e004000 0x1000>;
98*4882a593Smuzhiyun			interrupt-parent = <&vic0>;
99*4882a593Smuzhiyun			interrupts = <26>;
100*4882a593Smuzhiyun			clock-names = "watchdog";
101*4882a593Smuzhiyun			clocks = <&clocks PCLK_WDT>;
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		i2c0: i2c@7f004000 {
105*4882a593Smuzhiyun			compatible = "samsung,s3c2440-i2c";
106*4882a593Smuzhiyun			reg = <0x7f004000 0x1000>;
107*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
108*4882a593Smuzhiyun			interrupts = <18>;
109*4882a593Smuzhiyun			clock-names = "i2c";
110*4882a593Smuzhiyun			clocks = <&clocks PCLK_IIC0>;
111*4882a593Smuzhiyun			status = "disabled";
112*4882a593Smuzhiyun			#address-cells = <1>;
113*4882a593Smuzhiyun			#size-cells = <0>;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun		uart0: serial@7f005000 {
117*4882a593Smuzhiyun			compatible = "samsung,s3c6400-uart";
118*4882a593Smuzhiyun			reg = <0x7f005000 0x100>;
119*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
120*4882a593Smuzhiyun			interrupts = <5>;
121*4882a593Smuzhiyun			clock-names = "uart", "clk_uart_baud2",
122*4882a593Smuzhiyun					"clk_uart_baud3";
123*4882a593Smuzhiyun			clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124*4882a593Smuzhiyun					<&clocks SCLK_UART>;
125*4882a593Smuzhiyun			status = "disabled";
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		uart1: serial@7f005400 {
129*4882a593Smuzhiyun			compatible = "samsung,s3c6400-uart";
130*4882a593Smuzhiyun			reg = <0x7f005400 0x100>;
131*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
132*4882a593Smuzhiyun			interrupts = <6>;
133*4882a593Smuzhiyun			clock-names = "uart", "clk_uart_baud2",
134*4882a593Smuzhiyun					"clk_uart_baud3";
135*4882a593Smuzhiyun			clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
136*4882a593Smuzhiyun					<&clocks SCLK_UART>;
137*4882a593Smuzhiyun			status = "disabled";
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		uart2: serial@7f005800 {
141*4882a593Smuzhiyun			compatible = "samsung,s3c6400-uart";
142*4882a593Smuzhiyun			reg = <0x7f005800 0x100>;
143*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
144*4882a593Smuzhiyun			interrupts = <7>;
145*4882a593Smuzhiyun			clock-names = "uart", "clk_uart_baud2",
146*4882a593Smuzhiyun					"clk_uart_baud3";
147*4882a593Smuzhiyun			clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
148*4882a593Smuzhiyun					<&clocks SCLK_UART>;
149*4882a593Smuzhiyun			status = "disabled";
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun		uart3: serial@7f005c00 {
153*4882a593Smuzhiyun			compatible = "samsung,s3c6400-uart";
154*4882a593Smuzhiyun			reg = <0x7f005c00 0x100>;
155*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
156*4882a593Smuzhiyun			interrupts = <8>;
157*4882a593Smuzhiyun			clock-names = "uart", "clk_uart_baud2",
158*4882a593Smuzhiyun					"clk_uart_baud3";
159*4882a593Smuzhiyun			clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
160*4882a593Smuzhiyun					<&clocks SCLK_UART>;
161*4882a593Smuzhiyun			status = "disabled";
162*4882a593Smuzhiyun		};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun		pwm: pwm@7f006000 {
165*4882a593Smuzhiyun			compatible = "samsung,s3c6400-pwm";
166*4882a593Smuzhiyun			reg = <0x7f006000 0x1000>;
167*4882a593Smuzhiyun			interrupt-parent = <&vic0>;
168*4882a593Smuzhiyun			interrupts = <23>, <24>, <25>, <27>, <28>;
169*4882a593Smuzhiyun			clock-names = "timers";
170*4882a593Smuzhiyun			clocks = <&clocks PCLK_PWM>;
171*4882a593Smuzhiyun			samsung,pwm-outputs = <0>, <1>;
172*4882a593Smuzhiyun			#pwm-cells = <3>;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun		pinctrl0: pinctrl@7f008000 {
176*4882a593Smuzhiyun			compatible = "samsung,s3c64xx-pinctrl";
177*4882a593Smuzhiyun			reg = <0x7f008000 0x1000>;
178*4882a593Smuzhiyun			interrupt-parent = <&vic1>;
179*4882a593Smuzhiyun			interrupts = <21>;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun			pctrl_int_map: pinctrl-interrupt-map {
182*4882a593Smuzhiyun				interrupt-map = <0 &vic0 0>,
183*4882a593Smuzhiyun						<1 &vic0 1>,
184*4882a593Smuzhiyun						<2 &vic1 0>,
185*4882a593Smuzhiyun						<3 &vic1 1>;
186*4882a593Smuzhiyun				#address-cells = <0>;
187*4882a593Smuzhiyun				#size-cells = <0>;
188*4882a593Smuzhiyun				#interrupt-cells = <1>;
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			wakeup-interrupt-controller {
192*4882a593Smuzhiyun				compatible = "samsung,s3c64xx-wakeup-eint";
193*4882a593Smuzhiyun				interrupts = <0>, <1>, <2>, <3>;
194*4882a593Smuzhiyun				interrupt-parent = <&pctrl_int_map>;
195*4882a593Smuzhiyun			};
196*4882a593Smuzhiyun		};
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun#include "s3c64xx-pinctrl.dtsi"
201