1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Samsung S3C6410 based SMDK6410 board device tree source. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Device tree source file for Samsung SMDK6410 board which is based on 8*4882a593Smuzhiyun * Samsung's S3C6410 SoC. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 14*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include "s3c6410.dtsi" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/ { 19*4882a593Smuzhiyun model = "Samsung SMDK6410 board based on S3C6410"; 20*4882a593Smuzhiyun compatible = "samsung,mini6410", "samsung,s3c6410"; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun memory@50000000 { 23*4882a593Smuzhiyun device_type = "memory"; 24*4882a593Smuzhiyun reg = <0x50000000 0x8000000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun chosen { 28*4882a593Smuzhiyun bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun fin_pll: oscillator-0 { 32*4882a593Smuzhiyun compatible = "fixed-clock"; 33*4882a593Smuzhiyun clock-frequency = <12000000>; 34*4882a593Smuzhiyun clock-output-names = "fin_pll"; 35*4882a593Smuzhiyun #clock-cells = <0>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun xusbxti: oscillator-1 { 39*4882a593Smuzhiyun compatible = "fixed-clock"; 40*4882a593Smuzhiyun clock-output-names = "xusbxti"; 41*4882a593Smuzhiyun clock-frequency = <48000000>; 42*4882a593Smuzhiyun #clock-cells = <0>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun srom-cs1-bus@18000000 { 46*4882a593Smuzhiyun compatible = "simple-bus"; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun reg = <0x18000000 0x8000000>; 50*4882a593Smuzhiyun ranges; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ethernet@18000000 { 53*4882a593Smuzhiyun compatible = "smsc,lan9115"; 54*4882a593Smuzhiyun reg = <0x18000000 0x10000>; 55*4882a593Smuzhiyun interrupt-parent = <&gpn>; 56*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 57*4882a593Smuzhiyun phy-mode = "mii"; 58*4882a593Smuzhiyun reg-io-width = <4>; 59*4882a593Smuzhiyun smsc,force-internal-phy; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&clocks { 65*4882a593Smuzhiyun clocks = <&fin_pll>; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&sdhci0 { 69*4882a593Smuzhiyun pinctrl-names = "default"; 70*4882a593Smuzhiyun pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 71*4882a593Smuzhiyun bus-width = <4>; 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&uart0 { 76*4882a593Smuzhiyun pinctrl-names = "default"; 77*4882a593Smuzhiyun pinctrl-0 = <&uart0_data>, <&uart0_fctl>; 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&uart1 { 82*4882a593Smuzhiyun pinctrl-names = "default"; 83*4882a593Smuzhiyun pinctrl-0 = <&uart1_data>; 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&uart2 { 88*4882a593Smuzhiyun pinctrl-names = "default"; 89*4882a593Smuzhiyun pinctrl-0 = <&uart2_data>; 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&uart3 { 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&uart3_data>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun}; 98