1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rv1126.dtsi" 8*4882a593Smuzhiyun#include "rv1126-ipc.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Rockchip RV1126 IPC2 DDR3 V10 Board"; 13*4882a593Smuzhiyun compatible = "rockchip,rv1126-ipc2-ddr3-v10", "rockchip,rv1126"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun adc-keys { 16*4882a593Smuzhiyun compatible = "adc-keys"; 17*4882a593Smuzhiyun io-channels = <&saradc 0>; 18*4882a593Smuzhiyun io-channel-names = "buttons"; 19*4882a593Smuzhiyun poll-interval = <100>; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun recovery { 23*4882a593Smuzhiyun label = "Volum_up"; 24*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 25*4882a593Smuzhiyun press-threshold-microvolt = <0>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun rk809_sound: rk809-sound { 30*4882a593Smuzhiyun compatible = "simple-audio-card"; 31*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 32*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk809-codec"; 33*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 34*4882a593Smuzhiyun simple-audio-card,widgets = 35*4882a593Smuzhiyun "Microphone", "Mic Jack", 36*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 37*4882a593Smuzhiyun simple-audio-card,routing = 38*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 39*4882a593Smuzhiyun "IN1P", "Mic Jack", 40*4882a593Smuzhiyun "Headphone Jack", "HPOL", 41*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 42*4882a593Smuzhiyun simple-audio-card,cpu { 43*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun simple-audio-card,codec { 46*4882a593Smuzhiyun sound-dai = <&rk809_codec>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&csi_dphy0 { 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ports { 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <0>; 57*4882a593Smuzhiyun port@0 { 58*4882a593Smuzhiyun reg = <0>; 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <0>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 63*4882a593Smuzhiyun reg = <1>; 64*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 65*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun port@1 { 70*4882a593Smuzhiyun reg = <1>; 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 75*4882a593Smuzhiyun reg = <0>; 76*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&emmc { 83*4882a593Smuzhiyun bus-width = <8>; 84*4882a593Smuzhiyun cap-mmc-highspeed; 85*4882a593Smuzhiyun non-removable; 86*4882a593Smuzhiyun mmc-hs200-1_8v; 87*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 88*4882a593Smuzhiyun no-sdio; 89*4882a593Smuzhiyun no-sd; 90*4882a593Smuzhiyun /delete-property/ pinctrl-names; 91*4882a593Smuzhiyun /delete-property/ pinctrl-0; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&gmac { 96*4882a593Smuzhiyun phy-mode = "rmii"; 97*4882a593Smuzhiyun clock_in_out = "output"; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; 100*4882a593Smuzhiyun snps,reset-active-low; 101*4882a593Smuzhiyun snps,reset-delays-us = <0 50000 50000>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; 104*4882a593Smuzhiyun assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; 105*4882a593Smuzhiyun assigned-clock-rates = <50000000>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun pinctrl-names = "default"; 108*4882a593Smuzhiyun pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout_level0>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun phy-handle = <&phy>; 111*4882a593Smuzhiyun status = "okay"; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&i2c0 { 115*4882a593Smuzhiyun status = "okay"; 116*4882a593Smuzhiyun clock-frequency = <400000>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun rk809: pmic@20 { 119*4882a593Smuzhiyun compatible = "rockchip,rk809"; 120*4882a593Smuzhiyun reg = <0x20>; 121*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 122*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 123*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 124*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 125*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 126*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 127*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 128*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 129*4882a593Smuzhiyun rockchip,system-power-controller; 130*4882a593Smuzhiyun wakeup-source; 131*4882a593Smuzhiyun #clock-cells = <1>; 132*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 133*4882a593Smuzhiyun /* 0: rst the pmic, 1: rst regs (default in codes) */ 134*4882a593Smuzhiyun pmic-reset-func = <0>; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 137*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 138*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 139*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 140*4882a593Smuzhiyun vcc5-supply = <&vcc_buck5>; 141*4882a593Smuzhiyun vcc6-supply = <&vcc_buck5>; 142*4882a593Smuzhiyun vcc7-supply = <&vcc5v0_sys>; 143*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 144*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun pwrkey { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 151*4882a593Smuzhiyun gpio-controller; 152*4882a593Smuzhiyun #gpio-cells = <2>; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /omit-if-no-ref/ 155*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 156*4882a593Smuzhiyun pins = "gpio_slp"; 157*4882a593Smuzhiyun function = "pin_fun0"; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /omit-if-no-ref/ 161*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 162*4882a593Smuzhiyun pins = "gpio_slp"; 163*4882a593Smuzhiyun function = "pin_fun1"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /omit-if-no-ref/ 167*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 168*4882a593Smuzhiyun pins = "gpio_slp"; 169*4882a593Smuzhiyun function = "pin_fun2"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /omit-if-no-ref/ 173*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 174*4882a593Smuzhiyun pins = "gpio_slp"; 175*4882a593Smuzhiyun function = "pin_fun3"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun regulators { 180*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 181*4882a593Smuzhiyun regulator-always-on; 182*4882a593Smuzhiyun regulator-boot-on; 183*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 184*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 185*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 186*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 187*4882a593Smuzhiyun regulator-name = "vdd_logic"; 188*4882a593Smuzhiyun regulator-state-mem { 189*4882a593Smuzhiyun regulator-on-in-suspend; 190*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 195*4882a593Smuzhiyun regulator-always-on; 196*4882a593Smuzhiyun regulator-boot-on; 197*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 198*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 199*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 200*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 201*4882a593Smuzhiyun regulator-name = "vdd_arm"; 202*4882a593Smuzhiyun regulator-state-mem { 203*4882a593Smuzhiyun regulator-off-in-suspend; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 208*4882a593Smuzhiyun regulator-always-on; 209*4882a593Smuzhiyun regulator-boot-on; 210*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 211*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 212*4882a593Smuzhiyun regulator-state-mem { 213*4882a593Smuzhiyun regulator-on-in-suspend; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG4 { 218*4882a593Smuzhiyun regulator-always-on; 219*4882a593Smuzhiyun regulator-boot-on; 220*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 221*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 222*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 223*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 224*4882a593Smuzhiyun regulator-state-mem { 225*4882a593Smuzhiyun regulator-on-in-suspend; 226*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun vcc_buck5: DCDC_REG5 { 231*4882a593Smuzhiyun regulator-always-on; 232*4882a593Smuzhiyun regulator-boot-on; 233*4882a593Smuzhiyun regulator-min-microvolt = <2200000>; 234*4882a593Smuzhiyun regulator-max-microvolt = <2200000>; 235*4882a593Smuzhiyun regulator-name = "vcc_buck5"; 236*4882a593Smuzhiyun regulator-state-mem { 237*4882a593Smuzhiyun regulator-on-in-suspend; 238*4882a593Smuzhiyun regulator-suspend-microvolt = <2200000>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun vcc_0v8: LDO_REG1 { 243*4882a593Smuzhiyun regulator-always-on; 244*4882a593Smuzhiyun regulator-boot-on; 245*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 246*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 247*4882a593Smuzhiyun regulator-name = "vcc_0v8"; 248*4882a593Smuzhiyun regulator-state-mem { 249*4882a593Smuzhiyun regulator-off-in-suspend; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun vcc1v8_pmu: LDO_REG2 { 254*4882a593Smuzhiyun regulator-always-on; 255*4882a593Smuzhiyun regulator-boot-on; 256*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 257*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 258*4882a593Smuzhiyun regulator-name = "vcc1v8_pmu"; 259*4882a593Smuzhiyun regulator-state-mem { 260*4882a593Smuzhiyun regulator-on-in-suspend; 261*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun vdd0v8_pmu: LDO_REG3 { 266*4882a593Smuzhiyun regulator-always-on; 267*4882a593Smuzhiyun regulator-boot-on; 268*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 269*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 270*4882a593Smuzhiyun regulator-name = "vcc0v8_pmu"; 271*4882a593Smuzhiyun regulator-state-mem { 272*4882a593Smuzhiyun regulator-on-in-suspend; 273*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun vcc_1v8: LDO_REG4 { 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun regulator-boot-on; 280*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 281*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 282*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 283*4882a593Smuzhiyun regulator-state-mem { 284*4882a593Smuzhiyun regulator-on-in-suspend; 285*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun vcc_dovdd: LDO_REG5 { 290*4882a593Smuzhiyun regulator-boot-on; 291*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 292*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 293*4882a593Smuzhiyun regulator-name = "vcc_dovdd"; 294*4882a593Smuzhiyun regulator-state-mem { 295*4882a593Smuzhiyun regulator-off-in-suspend; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun vcc_dvdd: LDO_REG6 { 300*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 301*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 302*4882a593Smuzhiyun regulator-name = "vcc_dvdd"; 303*4882a593Smuzhiyun regulator-state-mem { 304*4882a593Smuzhiyun regulator-off-in-suspend; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun vcc_avdd: LDO_REG7 { 309*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 310*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 311*4882a593Smuzhiyun regulator-name = "vcc_avdd"; 312*4882a593Smuzhiyun regulator-state-mem { 313*4882a593Smuzhiyun regulator-off-in-suspend; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun vcc_ldo8: LDO_REG8 { 318*4882a593Smuzhiyun regulator-always-off; 319*4882a593Smuzhiyun regulator-boot-off; 320*4882a593Smuzhiyun regulator-name = "vcc_ldo8"; 321*4882a593Smuzhiyun regulator-state-mem { 322*4882a593Smuzhiyun regulator-off-in-suspend; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun vcc_ldo9: LDO_REG9 { 327*4882a593Smuzhiyun regulator-always-off; 328*4882a593Smuzhiyun regulator-boot-off; 329*4882a593Smuzhiyun regulator-name = "vcc_ldo9"; 330*4882a593Smuzhiyun regulator-state-mem { 331*4882a593Smuzhiyun regulator-off-in-suspend; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun vcc5v0_host: SWITCH_REG1 { 336*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun vcc_3v3: SWITCH_REG2 { 340*4882a593Smuzhiyun regulator-always-on; 341*4882a593Smuzhiyun regulator-boot-on; 342*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun rk809_codec: codec { 347*4882a593Smuzhiyun #sound-dai-cells = <0>; 348*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 349*4882a593Smuzhiyun clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 350*4882a593Smuzhiyun clock-names = "mclk"; 351*4882a593Smuzhiyun pinctrl-names = "default"; 352*4882a593Smuzhiyun assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 353*4882a593Smuzhiyun assigned-clock-parents = <&cru MCLK_I2S0_TX>; 354*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_mclk>; 355*4882a593Smuzhiyun hp-volume = <20>; 356*4882a593Smuzhiyun spk-volume = <3>; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun}; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun&i2c1 { 362*4882a593Smuzhiyun status = "okay"; 363*4882a593Smuzhiyun clock-frequency = <400000>; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun os04a10: os04a10@36 { 366*4882a593Smuzhiyun compatible = "ovti,os04a10"; 367*4882a593Smuzhiyun reg = <0x36>; 368*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 369*4882a593Smuzhiyun clock-names = "xvclk"; 370*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 371*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 372*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk0>; 373*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 374*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 375*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 376*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 377*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 378*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 379*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-OT1607-FV1"; 380*4882a593Smuzhiyun rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; 381*4882a593Smuzhiyun port { 382*4882a593Smuzhiyun ucam_out0: endpoint { 383*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 384*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun}; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun&i2s0_8ch { 392*4882a593Smuzhiyun status = "okay"; 393*4882a593Smuzhiyun #sound-dai-cells = <0>; 394*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 395*4882a593Smuzhiyun rockchip,i2s-rx-route = <3 1 2 0>; 396*4882a593Smuzhiyun pinctrl-names = "default"; 397*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_sclk_tx 398*4882a593Smuzhiyun &i2s0m0_lrck_tx 399*4882a593Smuzhiyun &i2s0m0_sdo0 400*4882a593Smuzhiyun &i2s0m0_sdo1_sdi3>; 401*4882a593Smuzhiyun}; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun&mdio { 404*4882a593Smuzhiyun phy: phy@0 { 405*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 406*4882a593Smuzhiyun reg = <0x0>; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun}; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun&pmu_io_domains { 411*4882a593Smuzhiyun status = "okay"; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun pmuio0-supply = <&vcc1v8_pmu>; 414*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_sys>; 415*4882a593Smuzhiyun vccio4-supply = <&vcc_1v8>; 416*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 417*4882a593Smuzhiyun vccio6-supply = <&vcc_3v3>; 418*4882a593Smuzhiyun vccio7-supply = <&vcc_1v8>; 419*4882a593Smuzhiyun}; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun&rkisp_vir0 { 422*4882a593Smuzhiyun status = "okay"; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun ports { 425*4882a593Smuzhiyun port@0 { 426*4882a593Smuzhiyun reg = <0>; 427*4882a593Smuzhiyun #address-cells = <1>; 428*4882a593Smuzhiyun #size-cells = <0>; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun isp_in: endpoint@0 { 431*4882a593Smuzhiyun reg = <0>; 432*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun}; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun&saradc { 439*4882a593Smuzhiyun status = "okay"; 440*4882a593Smuzhiyun vref-supply = <&vcc_1v8>; 441*4882a593Smuzhiyun}; 442