1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun chosen { 8*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff570000 loglevel=0 initcall_nr_threads=-1 initcall_debug=0 printk.devkmsg=on root=/dev/rd0 console=ttyFIQ0 snd_aloop.index=7 driver_async_probe=dwmmc_rockchip"; 9*4882a593Smuzhiyun }; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun vcc_3v3: vcc-3v3 { 12*4882a593Smuzhiyun compatible = "regulator-fixed"; 13*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 14*4882a593Smuzhiyun regulator-always-on; 15*4882a593Smuzhiyun regulator-boot-on; 16*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 17*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun vdd_arm: vdd-arm { 21*4882a593Smuzhiyun compatible = "pwm-regulator"; 22*4882a593Smuzhiyun pwms = <&pwm0 0 5000 1>; 23*4882a593Smuzhiyun regulator-name = "vdd_arm"; 24*4882a593Smuzhiyun regulator-min-microvolt = <720000>; 25*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 26*4882a593Smuzhiyun regulator-init-microvolt = <824000>; 27*4882a593Smuzhiyun regulator-always-on; 28*4882a593Smuzhiyun regulator-boot-on; 29*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 30*4882a593Smuzhiyun pwm-supply = <&vcc_3v3>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&cpu0 { 35*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&cpu_tsadc { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&display_subsystem { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&fiq_debugger { 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&mpp_srv { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&nandc { 55*4882a593Smuzhiyun /delete-property/ pinctrl-names; 56*4882a593Smuzhiyun /delete-property/ pinctrl-0; 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <0>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun nand@0 { 62*4882a593Smuzhiyun reg = <0>; 63*4882a593Smuzhiyun nand-bus-width = <8>; 64*4882a593Smuzhiyun nand-ecc-mode = "hw"; 65*4882a593Smuzhiyun nand-ecc-strength = <16>; 66*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&npu { 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&npu_tsadc { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&optee { 79*4882a593Smuzhiyun status = "disabled"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&otp { 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&pwm0 { 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun pinctrl-names = "active"; 89*4882a593Smuzhiyun pinctrl-0 = <&pwm0m0_pins_pull_down>; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&ramoops { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&rk_rga { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&rkisp { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&rkisp_vir0 { 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&rkisp_mmu { 109*4882a593Smuzhiyun status = "disabled"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&rkispp { 113*4882a593Smuzhiyun rockchip,restart-monitor-en; 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&rkispp_vir0 { 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&rkispp_mmu { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&rkvenc { 126*4882a593Smuzhiyun status = "okay"; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&rkvenc_mmu { 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&rng { 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&sfc { 138*4882a593Smuzhiyun /delete-property/ pinctrl-names; 139*4882a593Smuzhiyun /delete-property/ pinctrl-0; 140*4882a593Smuzhiyun status = "disabled"; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&u2phy0 { 144*4882a593Smuzhiyun status = "okay"; 145*4882a593Smuzhiyun u2phy_otg: otg-port { 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&usbdrd { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&usbdrd_dwc3 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun extcon = <&u2phy0>; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&vop { 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun}; 162