1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rv1126-38x38-v10-emmc.dts" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip RV1109 38x38 V10 EMMC DDR3 Board"; 12*4882a593Smuzhiyun compatible = "rockchip,rv1109-38x38-v10-emmc", "rockchip,rv1109"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&csi_dphy0 { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun ports { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun port@0 { 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun mipi_in_ucam2: endpoint@1 { 32*4882a593Smuzhiyun reg = <1>; 33*4882a593Smuzhiyun remote-endpoint = <&ucam_out2>; 34*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun port@1 { 38*4882a593Smuzhiyun reg = <1>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 43*4882a593Smuzhiyun reg = <0>; 44*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_input>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&i2c1 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun clock-frequency = <400000>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /delete-node/ imx415@1a ; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun imx335: imx335@1a { 57*4882a593Smuzhiyun compatible = "sony,imx335"; 58*4882a593Smuzhiyun reg = <0x1a>; 59*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 60*4882a593Smuzhiyun clock-names = "xvclk"; 61*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 62*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 63*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk0>; 64*4882a593Smuzhiyun avdd-supply = <&vcc3v3_sys>; 65*4882a593Smuzhiyun dovdd-supply = <&vcc_1v8>; 66*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 67*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 69*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 70*4882a593Smuzhiyun rockchip,camera-module-name = "MTV4-IR-E-P"; 71*4882a593Smuzhiyun rockchip,camera-module-lens-name = "40IRC-4MP-F16"; 72*4882a593Smuzhiyun ir-cut = <&cam_ircut0>; 73*4882a593Smuzhiyun flash-leds = <&flash_ir>; 74*4882a593Smuzhiyun port { 75*4882a593Smuzhiyun ucam_out2: endpoint { 76*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam2>; 77*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82