1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rv1106.dtsi" 9*4882a593Smuzhiyun#include "rv1106-evb.dtsi" 10*4882a593Smuzhiyun#include "rv1106-thunder-boot-spi-nor.dtsi" 11*4882a593Smuzhiyun#include "rv1106-smd-cam.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Rockchip RV1106G Smart Door Lock RMSL V10 Board"; 15*4882a593Smuzhiyun compatible = "rockchip,rv1106g-smart-door-lock-rmsl-v10", "rockchip,rv1106"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* rkaiq_prd_type: 1 for one camera, 2 for multi camera */ 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun acodec_sound: acodec-sound { 23*4882a593Smuzhiyun compatible = "simple-audio-card"; 24*4882a593Smuzhiyun simple-audio-card,name = "rv1106-acodec"; 25*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 26*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 27*4882a593Smuzhiyun simple-audio-card,cpu { 28*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun simple-audio-card,codec { 31*4882a593Smuzhiyun sound-dai = <&acodec>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun vcc_1v8: vcc-1v8 { 36*4882a593Smuzhiyun compatible = "regulator-fixed"; 37*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 38*4882a593Smuzhiyun regulator-always-on; 39*4882a593Smuzhiyun regulator-boot-on; 40*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 41*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun vcc_3v3: vcc-3v3 { 45*4882a593Smuzhiyun compatible = "regulator-fixed"; 46*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 47*4882a593Smuzhiyun regulator-always-on; 48*4882a593Smuzhiyun regulator-boot-on; 49*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun vdd_arm: vdd-arm { 54*4882a593Smuzhiyun compatible = "pwm-regulator"; 55*4882a593Smuzhiyun pwms = <&pwm0 0 5000 1>; 56*4882a593Smuzhiyun regulator-name = "vdd_arm"; 57*4882a593Smuzhiyun regulator-min-microvolt = <724000>; 58*4882a593Smuzhiyun regulator-max-microvolt = <1078000>; 59*4882a593Smuzhiyun regulator-init-microvolt = <950000>; 60*4882a593Smuzhiyun regulator-always-on; 61*4882a593Smuzhiyun regulator-boot-on; 62*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 66*4882a593Smuzhiyun compatible = "wlan-platdata"; 67*4882a593Smuzhiyun wifi_chip_type = "Hi3861L"; 68*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 69*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&acodec { 75*4882a593Smuzhiyun #sound-dai-cells = <0>; 76*4882a593Smuzhiyun pa-ctl-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&cpu0 { 81*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&dsm { 85*4882a593Smuzhiyun status = "disabled"; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&emmc { 89*4882a593Smuzhiyun status = "disabled"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&fiq_debugger { 93*4882a593Smuzhiyun rockchip,baudrate = <1500000>; 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&uart2m1_xfer>; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&gmac { 99*4882a593Smuzhiyun status = "disabled"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&pinctrl { 103*4882a593Smuzhiyun mcu { 104*4882a593Smuzhiyun /omit-if-no-ref/ 105*4882a593Smuzhiyun mcu_wake_det: mcu-wake-det { 106*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun pow_hold: pow-hold { 112*4882a593Smuzhiyun rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&pwm0 { 117*4882a593Smuzhiyun status = "okay"; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&sdmmc { 121*4882a593Smuzhiyun max-frequency = <50000000>; 122*4882a593Smuzhiyun bus-width = <1>; 123*4882a593Smuzhiyun cap-sd-highspeed; 124*4882a593Smuzhiyun cap-sdio-irq; 125*4882a593Smuzhiyun keep-power-in-suspend; 126*4882a593Smuzhiyun non-removable; 127*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 128*4882a593Smuzhiyun supports-sdio; 129*4882a593Smuzhiyun supports-chip-alive; 130*4882a593Smuzhiyun //logic-remove-card; 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_cmd &sdmmc0_clk &sdmmc0_bus4>; 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&sfc { 137*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_SFC>; 138*4882a593Smuzhiyun assigned-clock-rates = <125000000>; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun flash@0 { 142*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 143*4882a593Smuzhiyun reg = <0>; 144*4882a593Smuzhiyun spi-max-frequency = <125000000>; 145*4882a593Smuzhiyun spi-rx-bus-width = <4>; 146*4882a593Smuzhiyun spi-tx-bus-width = <1>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&thunder_boot_service { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&u2phy_otg { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&uart0 { 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161