1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1106.dtsi" 9#include "rv1106-evb-v10.dtsi" 10#include "rv1106-thunder-boot-spi-nor.dtsi" 11 12/ { 13 model = "Rockchip RV1106G EVB2 V10 Board With Dual Camera"; 14 compatible = "rockchip,rv1106g-evb2-v10-dual-camera", "rockchip,rv1106"; 15 16 chosen { 17 bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; 18 }; 19 20 vcc_1v8: vcc-1v8 { 21 compatible = "regulator-fixed"; 22 regulator-name = "vcc_1v8"; 23 regulator-always-on; 24 regulator-boot-on; 25 regulator-min-microvolt = <1800000>; 26 regulator-max-microvolt = <1800000>; 27 }; 28 29 vcc_3v3: vcc-3v3 { 30 compatible = "regulator-fixed"; 31 regulator-name = "vcc_3v3"; 32 regulator-always-on; 33 regulator-boot-on; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 }; 37 38 vcc3v3_sd: vcc3v3-sd { 39 compatible = "regulator-fixed"; 40 gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; 41 regulator-name = "vcc3v3_sd"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&sdmmc_pwren>; 46 }; 47}; 48 49&csi2_dphy_hw { 50 status = "okay"; 51}; 52 53&csi2_dphy1 { 54 status = "okay"; 55 56 ports { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 port@0 { 61 reg = <0>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 csi_dphy_input0: endpoint@0 { 66 reg = <0>; 67 remote-endpoint = <&sc301iot_out>; 68 data-lanes = <1 2>; 69 }; 70 }; 71 72 port@1 { 73 reg = <1>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 csi_dphy_output0: endpoint@0 { 78 reg = <0>; 79 remote-endpoint = <&mipi0_csi2_input>; 80 }; 81 }; 82 }; 83}; 84 85&csi2_dphy2 { 86 status = "okay"; 87 88 ports { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 port@0 { 93 reg = <0>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 csi_dphy_input1: endpoint@0 { 98 reg = <0>; 99 remote-endpoint = <&sc230ai_out>; 100 data-lanes = <1 2>; 101 }; 102 }; 103 104 port@1 { 105 reg = <1>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 csi_dphy_output1: endpoint@0 { 110 reg = <0>; 111 remote-endpoint = <&mipi1_csi2_input>; 112 }; 113 }; 114 }; 115}; 116 117&emmc { 118 status = "disabled"; 119}; 120 121&fiq_debugger { 122 rockchip,baudrate = <1500000>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&uart2m1_xfer>; 125}; 126 127&i2c4 { 128 rockchip,amp-shared; 129 130 sc230ai: sc230ai@30 { 131 compatible = "smartsens,sc230ai"; 132 status = "okay"; 133 reg = <0x30>; 134 clocks = <&cru MCLK_REF_MIPI1>; 135 clock-names = "xvclk"; 136 reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&mipi_refclk_out1>; 139 rockchip,camera-module-index = <1>; 140 rockchip,camera-module-facing = "back"; 141 rockchip,camera-module-name = "CMK-OT2350-PC1"; 142 rockchip,camera-module-lens-name = "65IRC-F16"; 143 port { 144 sc230ai_out: endpoint { 145 remote-endpoint = <&csi_dphy_input1>; 146 data-lanes = <1 2>; 147 }; 148 }; 149 }; 150 151 sc301iot: sc301iot@32 { 152 compatible = "smartsens,SC301IOT"; 153 status = "okay"; 154 reg = <0x32>; 155 clocks = <&cru MCLK_REF_MIPI0>; 156 clock-names = "xvclk"; 157 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 158 pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&mipi_refclk_out0>; 161 rockchip,camera-module-index = <0>; 162 rockchip,camera-module-facing = "back"; 163 rockchip,camera-module-name = "CMK-OT2349-PC1"; 164 rockchip,camera-module-lens-name = "65IRC-F20"; 165 port { 166 sc301iot_out: endpoint { 167 remote-endpoint = <&csi_dphy_input0>; 168 data-lanes = <1 2>; 169 }; 170 }; 171 }; 172}; 173 174&mipi0_csi2 { 175 status = "okay"; 176 177 ports { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 port@0 { 182 reg = <0>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 mipi0_csi2_input: endpoint@1 { 187 reg = <1>; 188 remote-endpoint = <&csi_dphy_output0>; 189 }; 190 }; 191 192 port@1 { 193 reg = <1>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 mipi0_csi2_output: endpoint@0 { 198 reg = <0>; 199 remote-endpoint = <&cif_mipi0_in>; 200 }; 201 }; 202 }; 203}; 204 205&mipi1_csi2 { 206 status = "okay"; 207 208 ports { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 port@0 { 213 reg = <0>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 217 mipi1_csi2_input: endpoint@1 { 218 reg = <1>; 219 remote-endpoint = <&csi_dphy_output1>; 220 }; 221 }; 222 223 port@1 { 224 reg = <1>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 mipi1_csi2_output: endpoint@0 { 229 reg = <0>; 230 remote-endpoint = <&cif_mipi1_in>; 231 }; 232 }; 233 }; 234}; 235 236&mailbox { 237 status = "okay"; 238}; 239 240&rkcif { 241 status = "okay"; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&mipi_pins>; 244}; 245 246&rkcif_mipi_lvds { 247 status = "okay"; 248 memory-region-thunderboot = <&rkisp_thunderboot>; 249 250 port { 251 /* MIPI CSI-2 endpoint */ 252 cif_mipi0_in: endpoint { 253 remote-endpoint = <&mipi0_csi2_output>; 254 }; 255 }; 256}; 257 258&rkcif_mipi_lvds_sditf { 259 status = "okay"; 260 261 port { 262 /* MIPI CSI-2 endpoint */ 263 mipi_lvds_sditf: endpoint { 264 remote-endpoint = <&isp_in>; 265 }; 266 }; 267}; 268 269&rkcif_mipi_lvds1 { 270 status = "okay"; 271 memory-region-thunderboot = <&rkisp1_thunderboot>; 272 273 port { 274 /* MIPI CSI-2 endpoint */ 275 cif_mipi1_in: endpoint { 276 remote-endpoint = <&mipi1_csi2_output>; 277 }; 278 }; 279}; 280 281&rkcif_mipi_lvds1_sditf { 282 status = "okay"; 283 284 port { 285 /* MIPI CSI-2 endpoint */ 286 mipi_lvds1_sditf: endpoint { 287 remote-endpoint = <&isp_in1>; 288 }; 289 }; 290}; 291 292&rkisp { 293 status = "okay"; 294}; 295 296&rkisp_vir0 { 297 status = "okay"; 298 memory-region-thunderboot = <&rkisp_thunderboot>; 299 300 port@0 { 301 isp_in: endpoint { 302 remote-endpoint = <&mipi_lvds_sditf>; 303 }; 304 }; 305}; 306 307&rkisp_vir1 { 308 status = "okay"; 309 memory-region-thunderboot = <&rkisp_thunderboot>; 310 311 port@0 { 312 isp_in1: endpoint { 313 remote-endpoint = <&mipi_lvds1_sditf>; 314 }; 315 }; 316}; 317 318&thunder_boot_service { 319 status = "okay"; 320}; 321 322&meta{ 323 /* reg's offset MUST match with RTOS */ 324 reg = <0x00800000 0xb0000>; 325}; 326 327&rkisp_thunderboot { 328 /* reg's offset MUST match with RTOS */ 329 /* 330 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) 331 * e.g. 2048x1536: 0xf00000 332 * 0x008b0000 = (meta's reg offset) + (meta's reg size) 333 * = 0x00800000 + 0xb0000 334 */ 335 reg = <0x008b0000 0xf00000>; 336}; 337 338&ramdisk_r { 339 reg = <0x17b0000 (10 * 0x00100000)>; 340}; 341 342&ramdisk_c { 343 reg = <0x21b0000 (5 * 0x00100000)>; 344}; 345 346&rkisp1_thunderboot { 347 /* 348 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) 349 * e.g. 1920x1080: 0xa8c0000 350 * 0x26b0000 = (ramdisk_c's reg offset) + (ramdisk_c's reg size) 351 * = 0x21b0000 + (5 * 0x00100000) 352 */ 353 reg = <0x26b0000 0xa8c000>; 354}; 355 356&pinctrl { 357 sdmmc { 358 /omit-if-no-ref/ 359 sdmmc_pwren: sdmmc-pwren { 360 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 361 }; 362 }; 363}; 364 365&pwm10 { 366 status = "okay"; 367}; 368 369&pwm11 { 370 status = "okay"; 371}; 372 373&sdio { 374 max-frequency = <50000000>; 375 bus-width = <1>; 376 cap-sd-highspeed; 377 cap-sdio-irq; 378 keep-power-in-suspend; 379 non-removable; 380 rockchip,default-sample-phase = <90>; 381 no-sd; 382 no-mmc; 383 supports-sdio; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>; 386 status = "okay"; 387}; 388 389&sdmmc { 390 max-frequency = <200000000>; 391 no-sdio; 392 no-mmc; 393 bus-width = <4>; 394 cap-mmc-highspeed; 395 cap-sd-highspeed; 396 disable-wp; 397 pinctrl-names = "normal", "idle"; 398 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 399 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; 400 vmmc-supply = <&vcc3v3_sd>; 401 status = "okay"; 402}; 403 404&sfc { 405 assigned-clocks = <&cru SCLK_SFC>; 406 assigned-clock-rates = <125000000>; 407 status = "okay"; 408 409 flash@0 { 410 compatible = "jedec,spi-nor"; 411 reg = <0>; 412 spi-max-frequency = <125000000>; 413 spi-rx-bus-width = <4>; 414 spi-tx-bus-width = <1>; 415 }; 416}; 417 418&usbdrd_dwc3 { 419 dr_mode = "peripheral"; 420}; 421