1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/media-bus-format.h> 7 8/ { 9 reserved-memory { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 ranges; 13 14 linux,cma { 15 compatible = "shared-dma-pool"; 16 inactive; 17 reusable; 18 size = <0x1000000>; 19 linux,cma-default; 20 }; 21 }; 22}; 23 24&display_subsystem { 25 status = "okay"; 26}; 27 28&i2c0 { 29 clock-frequency = <400000>; 30 status = "okay"; 31 32 sii9022: sii9022@39 { 33 compatible = "sil,sii9022"; 34 reg = <0x39>; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&sii902x_hdmi_int>; 37 interrupt-parent = <&gpio1>; 38 interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>; 39 reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 40 enable-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 41 bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 42 43 ports { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 port@0 { 48 reg = <0>; 49 50 sii9022_in_rgb: endpoint { 51 remote-endpoint = <&rgb_out_sii9022>; 52 }; 53 }; 54 }; 55 }; 56}; 57 58&pinctrl { 59 sii902x { 60 sii902x_hdmi_int: sii902x-hdmi-int { 61 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 62 }; 63 }; 64}; 65 66&rgb { 67 status = "okay"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&lcd_pins>; 70 71 ports { 72 port@1 { 73 reg = <1>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 rgb_out_sii9022: endpoint@0 { 78 reg = <0>; 79 remote-endpoint = <&sii9022_in_rgb>; 80 }; 81 }; 82 }; 83}; 84 85&rgb_in_vop { 86 status = "okay"; 87}; 88 89/* 90 * The pins of sdmmc1 and lcd are multiplexed 91 */ 92&sdio { 93 status = "disabled"; 94}; 95 96&sdio_pwrseq { 97 status = "disabled"; 98}; 99 100&vop { 101 status = "okay"; 102}; 103