1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1103.dtsi" 9#include "rv1106-thunder-boot-spi-nor.dtsi" 10 11/ { 12 model = "Rockchip RV1103G RMSL311 DLOC Board"; 13 compatible = "rockchip,rv1103g-rmsl311-dloc-v10", "rockchip,rv1103"; 14 15 chosen { 16 bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; 17 }; 18 19 vcc_1v8: vcc-1v8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "vcc_1v8"; 22 regulator-always-on; 23 regulator-boot-on; 24 regulator-min-microvolt = <1800000>; 25 regulator-max-microvolt = <1800000>; 26 }; 27 28 vcc_3v3: vcc-3v3 { 29 compatible = "regulator-fixed"; 30 regulator-name = "vcc_3v3"; 31 regulator-always-on; 32 regulator-boot-on; 33 regulator-min-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>; 35 }; 36 37 vdd_arm: vdd-arm { 38 compatible = "pwm-regulator"; 39 pwms = <&pwm0 0 5000 1>; 40 regulator-name = "vdd_arm"; 41 regulator-min-microvolt = <724000>; 42 regulator-max-microvolt = <1078000>; 43 regulator-init-microvolt = <950000>; 44 regulator-always-on; 45 regulator-boot-on; 46 regulator-settling-time-up-us = <250>; 47 }; 48}; 49 50&csi2_dphy_hw { 51 status = "okay"; 52}; 53 54&csi2_dphy1 { 55 status = "okay"; 56 ports { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 port@0 { 61 reg = <0>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 dphy1_in: endpoint@1 { 66 reg = <1>; 67 remote-endpoint = <&sc035gs_out>; 68 data-lanes = <1 2>; 69 }; 70 }; 71 72 port@1 { 73 reg = <1>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 dphy1_out: endpoint@1 { 77 reg = <1>; 78 remote-endpoint = <&mipi0_csi2_input>; 79 }; 80 }; 81 }; 82}; 83 84&fiq_debugger { 85 rockchip,irq-mode-enable = <1>; 86 status = "okay"; 87 rockchip,baudrate = <1500000>; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&uart2m1_xfer>; 90}; 91 92&i2c4 { 93 status = "okay"; 94 clock-frequency = <400000>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&i2c4m2_xfer>; 97 98 sc035gs: sc035gs@30 { 99 compatible = "smartsens,sc035gs"; 100 status = "okay"; 101 reg = <0x30>; 102 clocks = <&cru MCLK_REF_MIPI0>; 103 clock-names = "xvclk"; 104 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&mipi_refclk_out0>; 107 108 rockchip,camera-module-index = <0>; 109 rockchip,camera-module-facing = "back"; 110 rockchip,camera-module-name = "default"; 111 rockchip,camera-module-lens-name = "default"; 112 113 port { 114 sc035gs_out: endpoint { 115 remote-endpoint = <&dphy1_in>; 116 data-lanes = <1 2>; 117 }; 118 }; 119 }; 120 121 vcsel_rk803: vcsel_rk803@63 { 122 compatible = "rockchip,rk803"; 123 status = "okay"; 124 reg = <0x63>; 125 126 gpio-encc1-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; //Flood 127 gpio-encc2-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; //PRO 128 }; 129}; 130 131&memory { 132 reg = <0x00000000 0x04000000>; 133}; 134 135&mipi0_csi2 { 136 status = "okay"; 137 138 ports { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 142 port@0 { 143 reg = <0>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 mipi0_csi2_input: endpoint@1 { 148 reg = <1>; 149 remote-endpoint = <&dphy1_out>; 150 data-lanes = <1 2>; 151 }; 152 }; 153 154 port@1 { 155 reg = <1>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 159 mipi0_csi2_output: endpoint@0 { 160 reg = <0>; 161 remote-endpoint = <&cif_mipi0_in>; 162 data-lanes = <1 2>; 163 }; 164 }; 165 }; 166}; 167 168&npu { 169 status = "okay"; 170}; 171 172&pwm0 { 173 status = "okay"; 174}; 175 176&rga2 { 177 status = "okay"; 178}; 179 180&rkcif { 181 status = "okay"; 182}; 183 184&rkcif_mipi_lvds { 185 status = "okay"; 186 187 port { 188 /* MIPI CSI-2 endpoint */ 189 cif_mipi0_in: endpoint { 190 remote-endpoint = <&mipi0_csi2_output>; 191 data-lanes = <1 2>; 192 }; 193 }; 194}; 195 196&rkcif_mipi_lvds_sditf { 197 status = "okay"; 198 199 port { 200 /* MIPI CSI-2 endpoint */ 201 mipi_lvds0_sditf: endpoint { 202 remote-endpoint = <&isp0_in>; 203 data-lanes = <1 2>; 204 }; 205 }; 206}; 207 208&rkisp { 209 status = "okay"; 210 211 pinctrl-names = "default"; 212 pinctrl-0 = <&mipi_pins>; 213 214 max-input = <640 480 30>; 215}; 216 217&rkisp_vir0 { 218 status = "okay"; 219 220 ports { 221 port@0 { 222 isp0_in: endpoint { 223 remote-endpoint = <&mipi_lvds0_sditf>; 224 }; 225 }; 226 }; 227}; 228 229&rkisp_vir1 { 230 status = "okay"; 231}; 232 233&rng { 234 status = "okay"; 235}; 236 237&saradc { 238 status = "okay"; 239 vref-supply = <&vcc_1v8>; 240}; 241 242&sfc { 243 assigned-clocks = <&cru SCLK_SFC>; 244 assigned-clock-rates = <125000000>; 245 status = "okay"; 246 247 flash@0 { 248 compatible = "jedec,spi-nor"; 249 reg = <0>; 250 spi-max-frequency = <125000000>; 251 spi-rx-bus-width = <4>; 252 spi-tx-bus-width = <1>; 253 }; 254}; 255 256&tsadc { 257 status = "okay"; 258}; 259 260&u2phy { 261 status = "okay"; 262}; 263 264&u2phy_otg { 265 status = "okay"; 266}; 267 268&uart5 { 269 status = "okay"; 270}; 271 272&usbdrd { 273 status = "okay"; 274}; 275 276&usbdrd_dwc3 { 277 extcon = <&u2phy>; 278 status = "okay"; 279}; 280