1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rv1106-evb.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk0p5 rootfstype=ext4 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0"; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun acodec_sound: acodec-sound { 14*4882a593Smuzhiyun compatible = "simple-audio-card"; 15*4882a593Smuzhiyun simple-audio-card,name = "rv1103-acodec"; 16*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 17*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 18*4882a593Smuzhiyun simple-audio-card,cpu { 19*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun simple-audio-card,codec { 22*4882a593Smuzhiyun sound-dai = <&acodec>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun vdd_arm: vdd-arm { 27*4882a593Smuzhiyun compatible = "pwm-regulator"; 28*4882a593Smuzhiyun pwms = <&pwm0 0 5000 1>; 29*4882a593Smuzhiyun regulator-name = "vdd_arm"; 30*4882a593Smuzhiyun regulator-min-microvolt = <724000>; 31*4882a593Smuzhiyun regulator-max-microvolt = <1078000>; 32*4882a593Smuzhiyun regulator-init-microvolt = <950000>; 33*4882a593Smuzhiyun regulator-always-on; 34*4882a593Smuzhiyun regulator-boot-on; 35*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&acodec { 40*4882a593Smuzhiyun #sound-dai-cells = <0>; 41*4882a593Smuzhiyun pa-ctl-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&cpu0 { 46*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&emmc { 50*4882a593Smuzhiyun bus-width = <4>; 51*4882a593Smuzhiyun cap-mmc-highspeed; 52*4882a593Smuzhiyun non-removable; 53*4882a593Smuzhiyun mmc-hs200-1_8v; 54*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 55*4882a593Smuzhiyun no-sdio; 56*4882a593Smuzhiyun no-sd; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&i2c4 { 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun clock-frequency = <400000>; 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun pinctrl-0 = <&i2c4m2_xfer>; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&i2s0_8ch { 68*4882a593Smuzhiyun #sound-dai-cells = <0>; 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&pwm0 { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&sdmmc { 77*4882a593Smuzhiyun max-frequency = <50000000>; 78*4882a593Smuzhiyun no-sdio; 79*4882a593Smuzhiyun no-mmc; 80*4882a593Smuzhiyun bus-width = <4>; 81*4882a593Smuzhiyun cap-mmc-highspeed; 82*4882a593Smuzhiyun cap-sd-highspeed; 83*4882a593Smuzhiyun disable-wp; 84*4882a593Smuzhiyun pinctrl-names = "normal", "idle"; 85*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 86*4882a593Smuzhiyun pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&sfc { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun flash@0 { 94*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 95*4882a593Smuzhiyun reg = <0>; 96*4882a593Smuzhiyun spi-max-frequency = <80000000>; 97*4882a593Smuzhiyun spi-rx-bus-width = <4>; 98*4882a593Smuzhiyun spi-tx-bus-width = <1>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101