xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun * Copyright (c) 2019 Radxa Limited
5*4882a593Smuzhiyun * Copyright (c) 2019 Amarula Solutions(India)
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
12*4882a593Smuzhiyun		compatible = "fixed-clock";
13*4882a593Smuzhiyun		clock-frequency = <125000000>;
14*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
15*4882a593Smuzhiyun		#clock-cells = <0>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	vcc12v_dcin: vcc12v-dcin-regulator {
19*4882a593Smuzhiyun		compatible = "regulator-fixed";
20*4882a593Smuzhiyun		regulator-name = "vcc12v_dcin";
21*4882a593Smuzhiyun		regulator-always-on;
22*4882a593Smuzhiyun		regulator-boot-on;
23*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
24*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys-regulator {
28*4882a593Smuzhiyun		compatible = "regulator-fixed";
29*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
30*4882a593Smuzhiyun		regulator-always-on;
31*4882a593Smuzhiyun		regulator-boot-on;
32*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
33*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
34*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	vbus_host: vbus-host {
38*4882a593Smuzhiyun		compatible = "regulator-fixed";
39*4882a593Smuzhiyun		pinctrl-names = "default";
40*4882a593Smuzhiyun		pinctrl-0 = <&usb1_en_oc>;
41*4882a593Smuzhiyun		regulator-name = "vbus_host"; /* HOST-5V */
42*4882a593Smuzhiyun		regulator-always-on;
43*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	vbus_typec: vbus-typec {
47*4882a593Smuzhiyun		compatible = "regulator-fixed";
48*4882a593Smuzhiyun		pinctrl-names = "default";
49*4882a593Smuzhiyun		pinctrl-0 = <&usb0_en_oc>;
50*4882a593Smuzhiyun		regulator-name = "vbus_typec";
51*4882a593Smuzhiyun		regulator-always-on;
52*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&gmac {
57*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
58*4882a593Smuzhiyun	clock_in_out = "input";
59*4882a593Smuzhiyun	phy-mode = "rgmii";
60*4882a593Smuzhiyun	pinctrl-names = "default";
61*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
62*4882a593Smuzhiyun	snps,reset-active-low;
63*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
64*4882a593Smuzhiyun	tx_delay = <0x28>;
65*4882a593Smuzhiyun	rx_delay = <0x11>;
66*4882a593Smuzhiyun	status = "okay";
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&hdmi {
70*4882a593Smuzhiyun	status = "okay";
71*4882a593Smuzhiyun};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun&pwm0 {
74*4882a593Smuzhiyun	status = "okay";
75*4882a593Smuzhiyun};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun&pwm2 {
78*4882a593Smuzhiyun	status = "okay";
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&sdmmc {
82*4882a593Smuzhiyun	bus-width = <4>;
83*4882a593Smuzhiyun	cap-mmc-highspeed;
84*4882a593Smuzhiyun	cap-sd-highspeed;
85*4882a593Smuzhiyun	disable-wp;
86*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
87*4882a593Smuzhiyun	pinctrl-names = "default";
88*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&uart0 {
93*4882a593Smuzhiyun	pinctrl-names = "default";
94*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&uart2 {
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&vopb {
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&vopb_mmu {
107*4882a593Smuzhiyun	status = "okay";
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&vopl {
111*4882a593Smuzhiyun	status = "okay";
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&vopl_mmu {
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun};
117