1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Google Veyron (and derivatives) fragment for sdmmc cards 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Google, Inc 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&io_domains { 9*4882a593Smuzhiyun sdcard-supply = <&vccio_sd>; 10*4882a593Smuzhiyun}; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun&pinctrl { 13*4882a593Smuzhiyun sdmmc { 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * We run sdmmc at max speed; bump up drive strength. 16*4882a593Smuzhiyun * We also have external pulls, so disable the internal ones. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun sdmmc_bus4: sdmmc-bus4 { 19*4882a593Smuzhiyun rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, 20*4882a593Smuzhiyun <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, 21*4882a593Smuzhiyun <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, 22*4882a593Smuzhiyun <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun sdmmc_clk: sdmmc-clk { 26*4882a593Smuzhiyun rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun sdmmc_cmd: sdmmc-cmd { 30*4882a593Smuzhiyun rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Builtin CD line is hooked to ground to prevent JTAG at boot 35*4882a593Smuzhiyun * (and also to get the voltage rail correct). 36*4882a593Smuzhiyun * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't 37*4882a593Smuzhiyun * think there's a card inserted 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun sdmmc_cd_disabled: sdmmc-cd-disabled { 40*4882a593Smuzhiyun rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* This is where we actually hook up CD */ 44*4882a593Smuzhiyun sdmmc_cd_pin: sdmmc-cd-pin { 45*4882a593Smuzhiyun rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&rk808 { 51*4882a593Smuzhiyun vcc9-supply = <&vcc_5v>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun regulators { 54*4882a593Smuzhiyun vccio_sd: LDO_REG4 { 55*4882a593Smuzhiyun regulator-name = "vccio_sd"; 56*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 57*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 58*4882a593Smuzhiyun regulator-state-mem { 59*4882a593Smuzhiyun regulator-off-in-suspend; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun vcc33_sd: LDO_REG5 { 64*4882a593Smuzhiyun regulator-name = "vcc33_sd"; 65*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 66*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 67*4882a593Smuzhiyun regulator-state-mem { 68*4882a593Smuzhiyun regulator-off-in-suspend; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&sdmmc { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun bus-width = <4>; 78*4882a593Smuzhiyun cap-mmc-highspeed; 79*4882a593Smuzhiyun cap-sd-highspeed; 80*4882a593Smuzhiyun card-detect-delay = <200>; 81*4882a593Smuzhiyun cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; 82*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 83*4882a593Smuzhiyun sd-uhs-sdr12; 84*4882a593Smuzhiyun sd-uhs-sdr25; 85*4882a593Smuzhiyun sd-uhs-sdr50; 86*4882a593Smuzhiyun sd-uhs-sdr104; 87*4882a593Smuzhiyun vmmc-supply = <&vcc33_sd>; 88*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 89*4882a593Smuzhiyun}; 90