1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Google Veyron Minnie Rev 0+ board device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Google, Inc 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include "rk3288-veyron-chromebook.dtsi" 10*4882a593Smuzhiyun#include "rk3288-veyron-broadcom-bluetooth.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Google Minnie"; 14*4882a593Smuzhiyun compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", 15*4882a593Smuzhiyun "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", 16*4882a593Smuzhiyun "google,veyron-minnie-rev0", "google,veyron-minnie", 17*4882a593Smuzhiyun "google,veyron", "rockchip,rk3288"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun volume_buttons: volume-buttons { 20*4882a593Smuzhiyun compatible = "gpio-keys"; 21*4882a593Smuzhiyun pinctrl-names = "default"; 22*4882a593Smuzhiyun pinctrl-0 = <&volum_down_l &volum_up_l>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun volum_down { 25*4882a593Smuzhiyun label = "Volum_down"; 26*4882a593Smuzhiyun gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; 27*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 28*4882a593Smuzhiyun debounce-interval = <100>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun volum_up { 32*4882a593Smuzhiyun label = "Volum_up"; 33*4882a593Smuzhiyun gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 35*4882a593Smuzhiyun debounce-interval = <100>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&backlight { 41*4882a593Smuzhiyun /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ 42*4882a593Smuzhiyun brightness-levels = <0 3 255>; 43*4882a593Smuzhiyun num-interpolated-steps = <252>; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&i2c_tunnel { 47*4882a593Smuzhiyun battery: bq27500@55 { 48*4882a593Smuzhiyun compatible = "ti,bq27500"; 49*4882a593Smuzhiyun reg = <0x55>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&i2c3 { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun clock-frequency = <400000>; 57*4882a593Smuzhiyun i2c-scl-falling-time-ns = <50>; 58*4882a593Smuzhiyun i2c-scl-rising-time-ns = <300>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun touchscreen@10 { 61*4882a593Smuzhiyun compatible = "elan,ekth3500"; 62*4882a593Smuzhiyun reg = <0x10>; 63*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 64*4882a593Smuzhiyun interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun pinctrl-0 = <&touch_int &touch_rst>; 67*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun vcc33-supply = <&vcc33_touch>; 69*4882a593Smuzhiyun vccio-supply = <&vcc33_touch>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&panel { 74*4882a593Smuzhiyun compatible = "auo,b101ean01"; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /delete-node/ panel-timing; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun panel-timing { 79*4882a593Smuzhiyun clock-frequency = <66666667>; 80*4882a593Smuzhiyun hactive = <1280>; 81*4882a593Smuzhiyun hfront-porch = <18>; 82*4882a593Smuzhiyun hback-porch = <21>; 83*4882a593Smuzhiyun hsync-len = <32>; 84*4882a593Smuzhiyun vactive = <800>; 85*4882a593Smuzhiyun vfront-porch = <4>; 86*4882a593Smuzhiyun vback-porch = <8>; 87*4882a593Smuzhiyun vsync-len = <18>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&rk808 { 92*4882a593Smuzhiyun pinctrl-names = "default"; 93*4882a593Smuzhiyun pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun regulators { 96*4882a593Smuzhiyun vcc33_touch: LDO_REG2 { 97*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 98*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 99*4882a593Smuzhiyun regulator-name = "vcc33_touch"; 100*4882a593Smuzhiyun regulator-state-mem { 101*4882a593Smuzhiyun regulator-off-in-suspend; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun vcc5v_touch: SWITCH_REG2 { 106*4882a593Smuzhiyun regulator-name = "vcc5v_touch"; 107*4882a593Smuzhiyun regulator-state-mem { 108*4882a593Smuzhiyun regulator-off-in-suspend; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&sdmmc { 115*4882a593Smuzhiyun disable-wp; 116*4882a593Smuzhiyun pinctrl-names = "default"; 117*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin 118*4882a593Smuzhiyun &sdmmc_bus4>; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&vcc_5v { 122*4882a593Smuzhiyun enable-active-high; 123*4882a593Smuzhiyun gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; 124*4882a593Smuzhiyun pinctrl-names = "default"; 125*4882a593Smuzhiyun pinctrl-0 = <&drv_5v>; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&vcc50_hdmi { 129*4882a593Smuzhiyun enable-active-high; 130*4882a593Smuzhiyun gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun pinctrl-0 = <&vcc50_hdmi_en>; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&gpio0 { 136*4882a593Smuzhiyun gpio-line-names = "PMIC_SLEEP_AP", 137*4882a593Smuzhiyun "DDRIO_PWROFF", 138*4882a593Smuzhiyun "DDRIO_RETEN", 139*4882a593Smuzhiyun "TS3A227E_INT_L", 140*4882a593Smuzhiyun "PMIC_INT_L", 141*4882a593Smuzhiyun "PWR_KEY_L", 142*4882a593Smuzhiyun "AP_LID_INT_L", 143*4882a593Smuzhiyun "EC_IN_RW", 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun "AC_PRESENT_AP", 146*4882a593Smuzhiyun /* 147*4882a593Smuzhiyun * RECOVERY_SW_L is Chrome OS ABI. Schematics call 148*4882a593Smuzhiyun * it REC_MODE_L. 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun "RECOVERY_SW_L", 151*4882a593Smuzhiyun "OTP_OUT", 152*4882a593Smuzhiyun "HOST1_PWR_EN", 153*4882a593Smuzhiyun "USBOTG_PWREN_H", 154*4882a593Smuzhiyun "AP_WARM_RESET_H", 155*4882a593Smuzhiyun "nFALUT2", 156*4882a593Smuzhiyun "I2C0_SDA_PMIC", 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun "I2C0_SCL_PMIC", 159*4882a593Smuzhiyun "SUSPEND_L", 160*4882a593Smuzhiyun "USB_INT"; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&gpio2 { 164*4882a593Smuzhiyun gpio-line-names = "CONFIG0", 165*4882a593Smuzhiyun "CONFIG1", 166*4882a593Smuzhiyun "CONFIG2", 167*4882a593Smuzhiyun "", 168*4882a593Smuzhiyun "", 169*4882a593Smuzhiyun "", 170*4882a593Smuzhiyun "", 171*4882a593Smuzhiyun "CONFIG3", 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun "PROCHOT#", 174*4882a593Smuzhiyun "EMMC_RST_L", 175*4882a593Smuzhiyun "", 176*4882a593Smuzhiyun "", 177*4882a593Smuzhiyun "BL_PWR_EN", 178*4882a593Smuzhiyun "AVDD_1V8_DISP_EN", 179*4882a593Smuzhiyun "TOUCH_INT", 180*4882a593Smuzhiyun "TOUCH_RST", 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun "I2C3_SCL_TP", 183*4882a593Smuzhiyun "I2C3_SDA_TP"; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&gpio3 { 187*4882a593Smuzhiyun gpio-line-names = "FLASH0_D0", 188*4882a593Smuzhiyun "FLASH0_D1", 189*4882a593Smuzhiyun "FLASH0_D2", 190*4882a593Smuzhiyun "FLASH0_D3", 191*4882a593Smuzhiyun "FLASH0_D4", 192*4882a593Smuzhiyun "FLASH0_D5", 193*4882a593Smuzhiyun "FLASH0_D6", 194*4882a593Smuzhiyun "FLASH0_D7", 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun "", 197*4882a593Smuzhiyun "", 198*4882a593Smuzhiyun "", 199*4882a593Smuzhiyun "", 200*4882a593Smuzhiyun "", 201*4882a593Smuzhiyun "", 202*4882a593Smuzhiyun "", 203*4882a593Smuzhiyun "", 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun "FLASH0_CS2/EMMC_CMD", 206*4882a593Smuzhiyun "", 207*4882a593Smuzhiyun "FLASH0_DQS/EMMC_CLKO"; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&gpio4 { 211*4882a593Smuzhiyun gpio-line-names = "", 212*4882a593Smuzhiyun "", 213*4882a593Smuzhiyun "", 214*4882a593Smuzhiyun "", 215*4882a593Smuzhiyun "", 216*4882a593Smuzhiyun "", 217*4882a593Smuzhiyun "", 218*4882a593Smuzhiyun "", 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun "", 221*4882a593Smuzhiyun "", 222*4882a593Smuzhiyun "", 223*4882a593Smuzhiyun "", 224*4882a593Smuzhiyun "", 225*4882a593Smuzhiyun "", 226*4882a593Smuzhiyun "", 227*4882a593Smuzhiyun "", 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun "UART0_RXD", 230*4882a593Smuzhiyun "UART0_TXD", 231*4882a593Smuzhiyun "UART0_CTS", 232*4882a593Smuzhiyun "UART0_RTS", 233*4882a593Smuzhiyun "SDIO0_D0", 234*4882a593Smuzhiyun "SDIO0_D1", 235*4882a593Smuzhiyun "SDIO0_D2", 236*4882a593Smuzhiyun "SDIO0_D3", 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun "SDIO0_CMD", 239*4882a593Smuzhiyun "SDIO0_CLK", 240*4882a593Smuzhiyun "dev_wake", 241*4882a593Smuzhiyun "", 242*4882a593Smuzhiyun "WIFI_ENABLE_H", 243*4882a593Smuzhiyun "BT_ENABLE_L", 244*4882a593Smuzhiyun "WIFI_HOST_WAKE", 245*4882a593Smuzhiyun "BT_HOST_WAKE"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&gpio5 { 249*4882a593Smuzhiyun gpio-line-names = "", 250*4882a593Smuzhiyun "", 251*4882a593Smuzhiyun "", 252*4882a593Smuzhiyun "", 253*4882a593Smuzhiyun "", 254*4882a593Smuzhiyun "", 255*4882a593Smuzhiyun "", 256*4882a593Smuzhiyun "", 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun "", 259*4882a593Smuzhiyun "", 260*4882a593Smuzhiyun "Volum_Up#", 261*4882a593Smuzhiyun "Volum_Down#", 262*4882a593Smuzhiyun "SPI0_CLK", 263*4882a593Smuzhiyun "SPI0_CS0", 264*4882a593Smuzhiyun "SPI0_TXD", 265*4882a593Smuzhiyun "SPI0_RXD", 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun "", 268*4882a593Smuzhiyun "", 269*4882a593Smuzhiyun "", 270*4882a593Smuzhiyun "VCC50_HDMI_EN"; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&gpio6 { 274*4882a593Smuzhiyun gpio-line-names = "I2S0_SCLK", 275*4882a593Smuzhiyun "I2S0_LRCK_RX", 276*4882a593Smuzhiyun "I2S0_LRCK_TX", 277*4882a593Smuzhiyun "I2S0_SDI", 278*4882a593Smuzhiyun "I2S0_SDO0", 279*4882a593Smuzhiyun "HP_DET_H", 280*4882a593Smuzhiyun "", 281*4882a593Smuzhiyun "INT_CODEC", 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun "I2S0_CLK", 284*4882a593Smuzhiyun "I2C2_SDA", 285*4882a593Smuzhiyun "I2C2_SCL", 286*4882a593Smuzhiyun "MICDET", 287*4882a593Smuzhiyun "", 288*4882a593Smuzhiyun "", 289*4882a593Smuzhiyun "", 290*4882a593Smuzhiyun "", 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun "SDMMC_D0", 293*4882a593Smuzhiyun "SDMMC_D1", 294*4882a593Smuzhiyun "SDMMC_D2", 295*4882a593Smuzhiyun "SDMMC_D3", 296*4882a593Smuzhiyun "SDMMC_CLK", 297*4882a593Smuzhiyun "SDMMC_CMD"; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&gpio7 { 301*4882a593Smuzhiyun gpio-line-names = "LCDC_BL", 302*4882a593Smuzhiyun "PWM_LOG", 303*4882a593Smuzhiyun "BL_EN", 304*4882a593Smuzhiyun "TRACKPAD_INT", 305*4882a593Smuzhiyun "TPM_INT_H", 306*4882a593Smuzhiyun "SDMMC_DET_L", 307*4882a593Smuzhiyun /* 308*4882a593Smuzhiyun * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 309*4882a593Smuzhiyun * it FW_WP_AP. 310*4882a593Smuzhiyun */ 311*4882a593Smuzhiyun "AP_FLASH_WP_L", 312*4882a593Smuzhiyun "EC_INT", 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun "CPU_NMI", 315*4882a593Smuzhiyun "DVS_OK", 316*4882a593Smuzhiyun "SDMMC_WP", 317*4882a593Smuzhiyun "EDP_HPD", 318*4882a593Smuzhiyun "DVS1", 319*4882a593Smuzhiyun "nFALUT1", 320*4882a593Smuzhiyun "LCD_EN", 321*4882a593Smuzhiyun "DVS2", 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun "VCC5V_GOOD_H", 324*4882a593Smuzhiyun "I2C4_SDA_TP", 325*4882a593Smuzhiyun "I2C4_SCL_TP", 326*4882a593Smuzhiyun "I2C5_SDA_HDMI", 327*4882a593Smuzhiyun "I2C5_SCL_HDMI", 328*4882a593Smuzhiyun "5V_DRV", 329*4882a593Smuzhiyun "UART2_RXD", 330*4882a593Smuzhiyun "UART2_TXD"; 331*4882a593Smuzhiyun}; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun&gpio8 { 334*4882a593Smuzhiyun gpio-line-names = "RAM_ID0", 335*4882a593Smuzhiyun "RAM_ID1", 336*4882a593Smuzhiyun "RAM_ID2", 337*4882a593Smuzhiyun "RAM_ID3", 338*4882a593Smuzhiyun "I2C1_SDA_TPM", 339*4882a593Smuzhiyun "I2C1_SCL_TPM", 340*4882a593Smuzhiyun "SPI2_CLK", 341*4882a593Smuzhiyun "SPI2_CS0", 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun "SPI2_RXD", 344*4882a593Smuzhiyun "SPI2_TXD"; 345*4882a593Smuzhiyun}; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun&pinctrl { 348*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 349*4882a593Smuzhiyun pinctrl-0 = < 350*4882a593Smuzhiyun /* Common for sleep and wake, but no owners */ 351*4882a593Smuzhiyun &ddr0_retention 352*4882a593Smuzhiyun &ddrio_pwroff 353*4882a593Smuzhiyun &global_pwroff 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* Wake only */ 356*4882a593Smuzhiyun &suspend_l_wake 357*4882a593Smuzhiyun >; 358*4882a593Smuzhiyun pinctrl-1 = < 359*4882a593Smuzhiyun /* Common for sleep and wake, but no owners */ 360*4882a593Smuzhiyun &ddr0_retention 361*4882a593Smuzhiyun &ddrio_pwroff 362*4882a593Smuzhiyun &global_pwroff 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun /* Sleep only */ 365*4882a593Smuzhiyun &suspend_l_sleep 366*4882a593Smuzhiyun >; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun buck-5v { 369*4882a593Smuzhiyun drv_5v: drv-5v { 370*4882a593Smuzhiyun rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun buttons { 375*4882a593Smuzhiyun volum_down_l: volum-down-l { 376*4882a593Smuzhiyun rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun volum_up_l: volum-up-l { 380*4882a593Smuzhiyun rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun hdmi { 385*4882a593Smuzhiyun vcc50_hdmi_en: vcc50-hdmi-en { 386*4882a593Smuzhiyun rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun pmic { 391*4882a593Smuzhiyun dvs_1: dvs-1 { 392*4882a593Smuzhiyun rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun dvs_2: dvs-2 { 396*4882a593Smuzhiyun rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun prochot { 401*4882a593Smuzhiyun gpio_prochot: gpio-prochot { 402*4882a593Smuzhiyun rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun touchscreen { 407*4882a593Smuzhiyun touch_int: touch-int { 408*4882a593Smuzhiyun rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun touch_rst: touch-rst { 412*4882a593Smuzhiyun rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun}; 416