1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 3*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 4*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 5*4882a593Smuzhiyun * whole. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 8*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 9*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 10*4882a593Smuzhiyun * License, or (at your option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 13*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4882a593Smuzhiyun * GNU General Public License for more details. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Or, alternatively, 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 20*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 21*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 22*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 23*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 24*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 25*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 26*4882a593Smuzhiyun * conditions: 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 29*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 33*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 35*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 36*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 37*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 38*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun/dts-v1/; 42*4882a593Smuzhiyun#include <dt-bindings/clock/rockchip,rk808.h> 43*4882a593Smuzhiyun#include "rk3288.dtsi" 44*4882a593Smuzhiyun#include "rk3288-rkisp1.dtsi" 45*4882a593Smuzhiyun#include "rk3288-linux.dtsi" 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun/ { 48*4882a593Smuzhiyun compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun memory { 51*4882a593Smuzhiyun device_type = "memory"; 52*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x80000000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun wireless-bluetooth { 56*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 57*4882a593Smuzhiyun uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 58*4882a593Smuzhiyun pinctrl-names = "default","rts_gpio"; 59*4882a593Smuzhiyun pinctrl-0 = <&uart0_rts>; 60*4882a593Smuzhiyun pinctrl-1 = <&uart0_gpios>; 61*4882a593Smuzhiyun BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 63*4882a593Smuzhiyun BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>; 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun wireless-wlan { 68*4882a593Smuzhiyun compatible = "wlan-platdata"; 69*4882a593Smuzhiyun rockchip,grf = <&grf>; 70*4882a593Smuzhiyun wifi_chip_type = "ap6212"; 71*4882a593Smuzhiyun sdio_vref = <1800>; 72*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun ext_gmac: external-gmac-clock { 77*4882a593Smuzhiyun compatible = "fixed-clock"; 78*4882a593Smuzhiyun clock-frequency = <125000000>; 79*4882a593Smuzhiyun clock-output-names = "ext_gmac"; 80*4882a593Smuzhiyun #clock-cells = <0>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 84*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 85*4882a593Smuzhiyun clocks = <&rk808 RK808_CLKOUT1>; 86*4882a593Smuzhiyun clock-names = "ext_clock"; 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * On the module itself this is one of these (depending 92*4882a593Smuzhiyun * on the actual card populated): 93*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 94*4882a593Smuzhiyun * - PDN (power down when low) 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, 97*4882a593Smuzhiyun <&gpio4 27 GPIO_ACTIVE_LOW>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun gpio-keys { 101*4882a593Smuzhiyun compatible = "gpio-keys"; 102*4882a593Smuzhiyun #address-cells = <1>; 103*4882a593Smuzhiyun #size-cells = <0>; 104*4882a593Smuzhiyun autorepeat; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun pinctrl-names = "default"; 107*4882a593Smuzhiyun pinctrl-0 = <&pwrbtn>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun button@0 { 110*4882a593Smuzhiyun gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 111*4882a593Smuzhiyun linux,code = <116>; 112*4882a593Smuzhiyun label = "GPIO Key Power"; 113*4882a593Smuzhiyun linux,input-type = <1>; 114*4882a593Smuzhiyun gpio-key,wakeup = <1>; 115*4882a593Smuzhiyun debounce-interval = <100>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun gpio-leds { 120*4882a593Smuzhiyun compatible = "gpio-leds"; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun pwr-led { 123*4882a593Smuzhiyun gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 124*4882a593Smuzhiyun linux,default-trigger = "default-on"; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun act-led { 128*4882a593Smuzhiyun gpios=<&gpio1 24 GPIO_ACTIVE_HIGH>; 129*4882a593Smuzhiyun linux,default-trigger="mmc0"; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun led1-led { 133*4882a593Smuzhiyun gpios=<&gpio1 25 GPIO_ACTIVE_HIGH>; 134*4882a593Smuzhiyun linux,default-trigger="default-off"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun sound { 139*4882a593Smuzhiyun compatible = "simple-audio-card"; 140*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 141*4882a593Smuzhiyun simple-audio-card,name = "rockchip,miniarm-codec"; 142*4882a593Smuzhiyun simple-audio-card,mclk-fs = <512>; 143*4882a593Smuzhiyun simple-audio-card,cpu { 144*4882a593Smuzhiyun sound-dai = <&i2s>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun simple-audio-card,codec { 147*4882a593Smuzhiyun sound-dai = <&hdmi>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun vcc_sys: vsys-regulator { 152*4882a593Smuzhiyun compatible = "regulator-fixed"; 153*4882a593Smuzhiyun regulator-name = "vcc_sys"; 154*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 155*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 156*4882a593Smuzhiyun regulator-always-on; 157*4882a593Smuzhiyun regulator-boot-on; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from 162*4882a593Smuzhiyun * vcc_io directly. Those boards won't be able to power cycle SD cards 163*4882a593Smuzhiyun * but it shouldn't hurt to toggle this pin there anyway. 164*4882a593Smuzhiyun */ 165*4882a593Smuzhiyun vcc_sd: sdmmc-regulator { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; 168*4882a593Smuzhiyun pinctrl-names = "default"; 169*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_pwr>; 170*4882a593Smuzhiyun regulator-name = "vcc_sd"; 171*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 172*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 173*4882a593Smuzhiyun startup-delay-us = <100000>; 174*4882a593Smuzhiyun vin-supply = <&vcc_io>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun vcc_cam: vcc-camera { 178*4882a593Smuzhiyun compatible = "regulator-fixed"; 179*4882a593Smuzhiyun regulator-name = "vcc_cam"; 180*4882a593Smuzhiyun pinctrl-names = "default"; 181*4882a593Smuzhiyun pinctrl-0 = <&cam_pwr>; 182*4882a593Smuzhiyun enable-active-high; 183*4882a593Smuzhiyun gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; 184*4882a593Smuzhiyun regulator-always-on; 185*4882a593Smuzhiyun regulator-boot-on; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun ext_cam_clk: external-camera-clock { 189*4882a593Smuzhiyun compatible = "fixed-clock"; 190*4882a593Smuzhiyun clock-frequency = <25000000>; 191*4882a593Smuzhiyun clock-output-names = "CLK_CAMERA_25MHZ"; 192*4882a593Smuzhiyun #clock-cells = <0>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun xin32k: xin32k { 196*4882a593Smuzhiyun compatible = "fixed-clock"; 197*4882a593Smuzhiyun clock-frequency = <32768>; 198*4882a593Smuzhiyun clock-output-names = "xin32k"; 199*4882a593Smuzhiyun #clock-cells = <0>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&cpu0 { 204*4882a593Smuzhiyun cpu0-supply = <&vdd_cpu>; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&gmac { 208*4882a593Smuzhiyun phy-supply = <&vcc33_lan>; 209*4882a593Smuzhiyun phy-mode = "rgmii"; 210*4882a593Smuzhiyun clock_in_out = "input"; 211*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 7 0>; 212*4882a593Smuzhiyun snps,reset-active-low; 213*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 1000000>; 214*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_MAC>; 215*4882a593Smuzhiyun assigned-clock-parents = <&ext_gmac>; 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 218*4882a593Smuzhiyun tx_delay = <0x30>; 219*4882a593Smuzhiyun rx_delay = <0x10>; 220*4882a593Smuzhiyun status = "ok"; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun&gpu { 224*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&hdmi { 229*4882a593Smuzhiyun #address-cells = <1>; 230*4882a593Smuzhiyun #size-cells = <0>; 231*4882a593Smuzhiyun #sound-dai-cells = <0>; 232*4882a593Smuzhiyun status = "okay"; 233*4882a593Smuzhiyun /* Don't use vopl for HDMI */ 234*4882a593Smuzhiyun ports { 235*4882a593Smuzhiyun hdmi_in: port { 236*4882a593Smuzhiyun /delete-node/ endpoint@1; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&hevc_service { 242*4882a593Smuzhiyun status = "okay"; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun&i2c0 { 246*4882a593Smuzhiyun status = "okay"; 247*4882a593Smuzhiyun clock-frequency = <400000>; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun rk808: pmic@1b { 250*4882a593Smuzhiyun compatible = "rockchip,rk808"; 251*4882a593Smuzhiyun reg = <0x1b>; 252*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 253*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 254*4882a593Smuzhiyun pinctrl-names = "default"; 255*4882a593Smuzhiyun pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>; 256*4882a593Smuzhiyun dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, 257*4882a593Smuzhiyun <&gpio0 12 GPIO_ACTIVE_HIGH>; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun rockchip,system-power-controller; 260*4882a593Smuzhiyun wakeup-source; 261*4882a593Smuzhiyun #clock-cells = <1>; 262*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 265*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 266*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 267*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 268*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 269*4882a593Smuzhiyun vcc7-supply = <&vcc_sys>; 270*4882a593Smuzhiyun vcc8-supply = <&vcc_io>; 271*4882a593Smuzhiyun vcc9-supply = <&vcc_io>; 272*4882a593Smuzhiyun vcc10-supply = <&vcc_io>; 273*4882a593Smuzhiyun vcc11-supply = <&vcc_sys>; 274*4882a593Smuzhiyun vcc12-supply = <&vcc_io>; 275*4882a593Smuzhiyun vddio-supply = <&vcc_io>; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun regulators { 278*4882a593Smuzhiyun vdd_cpu: DCDC_REG1 { 279*4882a593Smuzhiyun regulator-always-on; 280*4882a593Smuzhiyun regulator-boot-on; 281*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 282*4882a593Smuzhiyun regulator-max-microvolt = <1450000>; 283*4882a593Smuzhiyun regulator-name = "vdd_arm"; 284*4882a593Smuzhiyun regulator-ramp-delay = <6000>; 285*4882a593Smuzhiyun regulator-state-mem { 286*4882a593Smuzhiyun regulator-off-in-suspend; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 291*4882a593Smuzhiyun regulator-always-on; 292*4882a593Smuzhiyun regulator-boot-on; 293*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 294*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 295*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 296*4882a593Smuzhiyun regulator-ramp-delay = <6000>; 297*4882a593Smuzhiyun regulator-state-mem { 298*4882a593Smuzhiyun regulator-on-in-suspend; 299*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 304*4882a593Smuzhiyun regulator-always-on; 305*4882a593Smuzhiyun regulator-boot-on; 306*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 307*4882a593Smuzhiyun regulator-state-mem { 308*4882a593Smuzhiyun regulator-on-in-suspend; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 313*4882a593Smuzhiyun regulator-always-on; 314*4882a593Smuzhiyun regulator-boot-on; 315*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 316*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 317*4882a593Smuzhiyun regulator-name = "vcc_io"; 318*4882a593Smuzhiyun regulator-state-mem { 319*4882a593Smuzhiyun regulator-on-in-suspend; 320*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun vcc18_ldo1: LDO_REG1 { 325*4882a593Smuzhiyun regulator-always-on; 326*4882a593Smuzhiyun regulator-boot-on; 327*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 328*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 329*4882a593Smuzhiyun regulator-name = "vcc18_ldo1"; 330*4882a593Smuzhiyun regulator-state-mem { 331*4882a593Smuzhiyun regulator-on-in-suspend; 332*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun vcc33_mipi: LDO_REG2 { 337*4882a593Smuzhiyun regulator-always-on; 338*4882a593Smuzhiyun regulator-boot-on; 339*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 340*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 341*4882a593Smuzhiyun regulator-name = "vcc33_mipi"; 342*4882a593Smuzhiyun regulator-state-mem { 343*4882a593Smuzhiyun regulator-off-in-suspend; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun vdd_10: LDO_REG3 { 348*4882a593Smuzhiyun regulator-always-on; 349*4882a593Smuzhiyun regulator-boot-on; 350*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 351*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 352*4882a593Smuzhiyun regulator-name = "vdd_10"; 353*4882a593Smuzhiyun regulator-state-mem { 354*4882a593Smuzhiyun regulator-on-in-suspend; 355*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun vcc18_codec: LDO_REG4 { 360*4882a593Smuzhiyun regulator-always-on; 361*4882a593Smuzhiyun regulator-boot-on; 362*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 363*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 364*4882a593Smuzhiyun regulator-name = "vcc18_codec"; 365*4882a593Smuzhiyun regulator-state-mem { 366*4882a593Smuzhiyun regulator-on-in-suspend; 367*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 372*4882a593Smuzhiyun regulator-always-on; 373*4882a593Smuzhiyun regulator-boot-on; 374*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 375*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 376*4882a593Smuzhiyun regulator-name = "vccio_sd"; 377*4882a593Smuzhiyun regulator-state-mem { 378*4882a593Smuzhiyun regulator-on-in-suspend; 379*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun vdd10_lcd: LDO_REG6 { 384*4882a593Smuzhiyun regulator-always-on; 385*4882a593Smuzhiyun regulator-boot-on; 386*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 387*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 388*4882a593Smuzhiyun regulator-name = "vdd10_lcd"; 389*4882a593Smuzhiyun regulator-state-mem { 390*4882a593Smuzhiyun regulator-on-in-suspend; 391*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun vcc_18: LDO_REG7 { 396*4882a593Smuzhiyun regulator-always-on; 397*4882a593Smuzhiyun regulator-boot-on; 398*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 399*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 400*4882a593Smuzhiyun regulator-name = "vcc_18"; 401*4882a593Smuzhiyun regulator-state-mem { 402*4882a593Smuzhiyun regulator-on-in-suspend; 403*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun vcc18_lcd: LDO_REG8 { 408*4882a593Smuzhiyun regulator-always-on; 409*4882a593Smuzhiyun regulator-boot-on; 410*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 411*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 412*4882a593Smuzhiyun regulator-name = "vcc18_lcd"; 413*4882a593Smuzhiyun regulator-state-mem { 414*4882a593Smuzhiyun regulator-on-in-suspend; 415*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun vcc33_sd: SWITCH_REG1 { 420*4882a593Smuzhiyun regulator-always-on; 421*4882a593Smuzhiyun regulator-boot-on; 422*4882a593Smuzhiyun regulator-name = "vcc33_sd"; 423*4882a593Smuzhiyun regulator-state-mem { 424*4882a593Smuzhiyun regulator-on-in-suspend; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun vcc33_lan: SWITCH_REG2 { 429*4882a593Smuzhiyun regulator-always-on; 430*4882a593Smuzhiyun regulator-boot-on; 431*4882a593Smuzhiyun regulator-name = "vcc33_lan"; 432*4882a593Smuzhiyun regulator-state-mem { 433*4882a593Smuzhiyun regulator-on-in-suspend; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun}; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun&i2c2 { 441*4882a593Smuzhiyun status = "okay"; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun camera0: ov5647@36 { 444*4882a593Smuzhiyun compatible = "ovti,ov5647"; 445*4882a593Smuzhiyun reg = <0x36>; 446*4882a593Smuzhiyun clocks = <&ext_cam_clk>; 447*4882a593Smuzhiyun status = "okay"; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun camera1: imx219@10 { 451*4882a593Smuzhiyun compatible = "sony,imx219"; 452*4882a593Smuzhiyun reg = <0x10>; 453*4882a593Smuzhiyun clocks = <&ext_cam_clk>; 454*4882a593Smuzhiyun status = "okay"; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun port { 457*4882a593Smuzhiyun imx219_out: endpoint { 458*4882a593Smuzhiyun remote-endpoint = <&imx219_in>; 459*4882a593Smuzhiyun data-lanes = <1 2>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun m24c08@50 { 465*4882a593Smuzhiyun compatible = "at,24c08"; 466*4882a593Smuzhiyun reg = <0x50>; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun}; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun&i2c3 { 471*4882a593Smuzhiyun status = "okay"; 472*4882a593Smuzhiyun}; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun&i2c4 { 475*4882a593Smuzhiyun status = "okay"; 476*4882a593Smuzhiyun}; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun&isp { 479*4882a593Smuzhiyun status = "okay"; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun port { 482*4882a593Smuzhiyun isp_mipi_in: endpoint { 483*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun}; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun&isp_mmu { 489*4882a593Smuzhiyun status = "okay"; 490*4882a593Smuzhiyun}; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun&mipi_phy_rx0 { 493*4882a593Smuzhiyun status = "okay"; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun ports { 496*4882a593Smuzhiyun #address-cells = <1>; 497*4882a593Smuzhiyun #size-cells = <0>; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun port@0 { 500*4882a593Smuzhiyun reg = <0>; 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun imx219_in: endpoint { 503*4882a593Smuzhiyun remote-endpoint = <&imx219_out>; 504*4882a593Smuzhiyun data-lanes = <1 2>; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun port@1 { 509*4882a593Smuzhiyun reg = <1>; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun dphy_rx0_out: endpoint { 512*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun}; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun&spi2 { 519*4882a593Smuzhiyun status = "okay"; 520*4882a593Smuzhiyun max-freq = <50000000>; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun spidev@0 { 523*4882a593Smuzhiyun compatible = "rockchip,spi_tinker"; 524*4882a593Smuzhiyun reg = <0>; 525*4882a593Smuzhiyun spi-max-frequency = <50000000>; 526*4882a593Smuzhiyun spi-cpha = <1>; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun spidev@1 { 530*4882a593Smuzhiyun compatible = "rockchip,spi_tinker"; 531*4882a593Smuzhiyun reg = <1>; 532*4882a593Smuzhiyun spi-max-frequency = <50000000>; 533*4882a593Smuzhiyun spi-cpha = <1>; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun}; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun&i2s { 538*4882a593Smuzhiyun #sound-dai-cells = <0>; 539*4882a593Smuzhiyun status = "okay"; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&io_domains { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun sdcard-supply = <&vccio_sd>; 546*4882a593Smuzhiyun wifi-supply = <&vcc_18>; 547*4882a593Smuzhiyun}; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun&sdio0 { 550*4882a593Smuzhiyun status = "okay"; 551*4882a593Smuzhiyun clock-frequency = <50000000>; 552*4882a593Smuzhiyun clock-freq-min-max = <200000 50000000>; 553*4882a593Smuzhiyun bus-width = <4>; 554*4882a593Smuzhiyun cap-sd-highspeed; 555*4882a593Smuzhiyun cap-sdio-irq; 556*4882a593Smuzhiyun disable-wp; 557*4882a593Smuzhiyun keep-power-in-suspend; 558*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 559*4882a593Smuzhiyun non-removable; 560*4882a593Smuzhiyun num-slots = <1>; 561*4882a593Smuzhiyun pinctrl-names = "default"; 562*4882a593Smuzhiyun pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 563*4882a593Smuzhiyun sd-uhs-sdr104; 564*4882a593Smuzhiyun no-sd; 565*4882a593Smuzhiyun no-mmc; 566*4882a593Smuzhiyun}; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun&pwm0 { 569*4882a593Smuzhiyun status = "okay"; 570*4882a593Smuzhiyun}; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun&saradc { 573*4882a593Smuzhiyun vref-supply = <&vcc18_ldo1>; 574*4882a593Smuzhiyun status ="okay"; 575*4882a593Smuzhiyun}; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun&sdmmc { 578*4882a593Smuzhiyun bus-width = <4>; 579*4882a593Smuzhiyun cap-mmc-highspeed; 580*4882a593Smuzhiyun cap-sd-highspeed; 581*4882a593Smuzhiyun sd-uhs-sdr12; 582*4882a593Smuzhiyun sd-uhs-sdr25; 583*4882a593Smuzhiyun sd-uhs-sdr50; 584*4882a593Smuzhiyun sd-uhs-sdr104; 585*4882a593Smuzhiyun card-detect-delay = <200>; 586*4882a593Smuzhiyun disable-wp; /* wp not hooked up */ 587*4882a593Smuzhiyun num-slots = <1>; 588*4882a593Smuzhiyun pinctrl-names = "default"; 589*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 590*4882a593Smuzhiyun status = "okay"; 591*4882a593Smuzhiyun no-sdio; 592*4882a593Smuzhiyun no-mmc; 593*4882a593Smuzhiyun vmmc-supply = <&vcc33_sd>; 594*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 595*4882a593Smuzhiyun}; 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun&tsadc { 598*4882a593Smuzhiyun rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 599*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 600*4882a593Smuzhiyun pinctrl-1 = <&otp_out>; 601*4882a593Smuzhiyun status = "okay"; 602*4882a593Smuzhiyun}; 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun&uart0 { 605*4882a593Smuzhiyun pinctrl-names = "default"; 606*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer>, <&uart0_cts>; 607*4882a593Smuzhiyun status = "okay"; 608*4882a593Smuzhiyun}; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun&uart1 { 611*4882a593Smuzhiyun status = "okay"; 612*4882a593Smuzhiyun}; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun&uart2 { 615*4882a593Smuzhiyun status = "okay"; 616*4882a593Smuzhiyun}; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun&uart3 { 619*4882a593Smuzhiyun status = "okay"; 620*4882a593Smuzhiyun}; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun&uart4 { 623*4882a593Smuzhiyun status = "okay"; 624*4882a593Smuzhiyun}; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun&usbphy { 627*4882a593Smuzhiyun status = "okay"; 628*4882a593Smuzhiyun}; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun&usb_host0_ehci { 631*4882a593Smuzhiyun no-relinquish-port; 632*4882a593Smuzhiyun status = "okay"; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&usb_host1 { 636*4882a593Smuzhiyun status = "okay"; 637*4882a593Smuzhiyun}; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun&usb_otg { 640*4882a593Smuzhiyun status= "okay"; 641*4882a593Smuzhiyun}; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun&vopb { 644*4882a593Smuzhiyun status = "okay"; 645*4882a593Smuzhiyun}; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun&vopb_mmu { 648*4882a593Smuzhiyun status = "okay"; 649*4882a593Smuzhiyun}; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun&vopl { 652*4882a593Smuzhiyun status = "okay"; 653*4882a593Smuzhiyun /* Don't use vopl for HDMI */ 654*4882a593Smuzhiyun vopl_out: port { 655*4882a593Smuzhiyun /delete-node/ endpoint@0; 656*4882a593Smuzhiyun }; 657*4882a593Smuzhiyun}; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun&vopl_mmu { 660*4882a593Smuzhiyun status = "okay"; 661*4882a593Smuzhiyun}; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun&vpu_service { 664*4882a593Smuzhiyun status = "okay"; 665*4882a593Smuzhiyun}; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun&wdt { 668*4882a593Smuzhiyun status = "okay"; 669*4882a593Smuzhiyun}; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun&pinctrl { 672*4882a593Smuzhiyun pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 673*4882a593Smuzhiyun drive-strength = <8>; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 677*4882a593Smuzhiyun bias-pull-up; 678*4882a593Smuzhiyun drive-strength = <8>; 679*4882a593Smuzhiyun }; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun backlight { 682*4882a593Smuzhiyun bl_en: bl-en { 683*4882a593Smuzhiyun rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun }; 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun buttons { 688*4882a593Smuzhiyun pwrbtn: pwrbtn { 689*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 690*4882a593Smuzhiyun }; 691*4882a593Smuzhiyun }; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun eth_phy { 694*4882a593Smuzhiyun eth_phy_pwr: eth-phy-pwr { 695*4882a593Smuzhiyun rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun pmic { 700*4882a593Smuzhiyun pmic_int: pmic-int { 701*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 702*4882a593Smuzhiyun }; 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun dvs_1: dvs-1 { 705*4882a593Smuzhiyun rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun dvs_2: dvs-2 { 709*4882a593Smuzhiyun rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun sdio-pwrseq { 714*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 715*4882a593Smuzhiyun rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 716*4882a593Smuzhiyun }; 717*4882a593Smuzhiyun chip_enable_h: chip-enable-h { 718*4882a593Smuzhiyun rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun }; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun sdmmc { 723*4882a593Smuzhiyun /* 724*4882a593Smuzhiyun * Default drive strength isn't enough to achieve even 725*4882a593Smuzhiyun * high-speed mode on EVB board so bump up to 8ma. 726*4882a593Smuzhiyun */ 727*4882a593Smuzhiyun sdmmc_bus4: sdmmc-bus4 { 728*4882a593Smuzhiyun rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, 729*4882a593Smuzhiyun <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, 730*4882a593Smuzhiyun <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, 731*4882a593Smuzhiyun <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; 732*4882a593Smuzhiyun }; 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun sdmmc_clk: sdmmc-clk { 735*4882a593Smuzhiyun rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; 736*4882a593Smuzhiyun }; 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun sdmmc_cmd: sdmmc-cmd { 739*4882a593Smuzhiyun rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun sdmmc_pwr: sdmmc-pwr { 743*4882a593Smuzhiyun rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun }; 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun usb { 748*4882a593Smuzhiyun host_vbus_drv: host-vbus-drv { 749*4882a593Smuzhiyun rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 750*4882a593Smuzhiyun }; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun pwr_3g: pwr-3g { 753*4882a593Smuzhiyun rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 754*4882a593Smuzhiyun }; 755*4882a593Smuzhiyun }; 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun wireless-bluetooth { 758*4882a593Smuzhiyun uart0_gpios: uart0-gpios { 759*4882a593Smuzhiyun rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun cam_pins { 764*4882a593Smuzhiyun cam_pwr: cam-pwr { 765*4882a593Smuzhiyun rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun }; 768*4882a593Smuzhiyun}; 769