1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 12*4882a593Smuzhiyun * License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Or, alternatively, 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 22*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 23*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 24*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 25*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 26*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 27*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 28*4882a593Smuzhiyun * conditions: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 31*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/dts-v1/; 44*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 45*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 46*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 47*4882a593Smuzhiyun#include "rk3288-firefly.dtsi" 48*4882a593Smuzhiyun#include "rk3288-android.dtsi" 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun/ { 51*4882a593Smuzhiyun model = "Firefly-RK3288"; 52*4882a593Smuzhiyun compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun chosen { 55*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff690000"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 59*4882a593Smuzhiyun clocks = <&rk808 1>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun wireless-bluetooth { 63*4882a593Smuzhiyun clocks = <&rk808 1>; 64*4882a593Smuzhiyun clock-names = "ext_clock"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /delete-node/ sdmmc-regulator; 68*4882a593Smuzhiyun vcc_sd: sdmmc-regulator { 69*4882a593Smuzhiyun compatible = "regulator-fixed"; 70*4882a593Smuzhiyun gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_pwr>; 73*4882a593Smuzhiyun regulator-name = "vcc_sd"; 74*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 75*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 76*4882a593Smuzhiyun startup-delay-us = <100000>; 77*4882a593Smuzhiyun vin-supply = <&vcc_io>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun vcc_lcd: vcc-lcd { 81*4882a593Smuzhiyun compatible = "regulator-fixed"; 82*4882a593Smuzhiyun regulator-boot-on; 83*4882a593Smuzhiyun enable-active-high; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun pinctrl-0 = <&lcd_en>; 86*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 87*4882a593Smuzhiyun vin-supply = <&vcc_io>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun sound: sound { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun compatible = "simple-audio-card"; 93*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 94*4882a593Smuzhiyun simple-audio-card,name = "rockchip,firefly-codec"; 95*4882a593Smuzhiyun simple-audio-card,mclk-fs = <512>; 96*4882a593Smuzhiyun simple-audio-card,widgets = 97*4882a593Smuzhiyun "Microphone", "Microphone Jack", 98*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 99*4882a593Smuzhiyun simple-audio-card,routing = 100*4882a593Smuzhiyun "MIC1", "Microphone Jack", 101*4882a593Smuzhiyun "MIC2", "Microphone Jack", 102*4882a593Smuzhiyun "Microphone Jack", "micbias1", 103*4882a593Smuzhiyun "Headphone Jack", "HPOL", 104*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun simple-audio-card,dai-link@0 { 107*4882a593Smuzhiyun format = "i2s"; 108*4882a593Smuzhiyun cpu { 109*4882a593Smuzhiyun sound-dai = <&i2s>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun codec { 113*4882a593Smuzhiyun sound-dai = <&es8323>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun simple-audio-card,dai-link@1 { 118*4882a593Smuzhiyun format = "i2s"; 119*4882a593Smuzhiyun cpu { 120*4882a593Smuzhiyun sound-dai = <&i2s>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun codec { 124*4882a593Smuzhiyun sound-dai = <&hdmi>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun spdif-sound { 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun compatible = "simple-audio-card"; 132*4882a593Smuzhiyun simple-audio-card,name = "ROCKCHIP,SPDIF"; 133*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 134*4882a593Smuzhiyun simple-audio-card,cpu { 135*4882a593Smuzhiyun sound-dai = <&spdif>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun simple-audio-card,codec { 138*4882a593Smuzhiyun sound-dai = <&spdif_out>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun backlight: backlight { 143*4882a593Smuzhiyun pwms = <&pwm1 0 1000000 0>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun hdmi_analog_sound: hdmi-analog-sound { 147*4882a593Smuzhiyun status = "disabled"; 148*4882a593Smuzhiyun rockchip,codec = <&es8323>, <&hdmi>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun reserved-memory { 152*4882a593Smuzhiyun ramoops: ramoops@8000000 { 153*4882a593Smuzhiyun compatible = "ramoops"; 154*4882a593Smuzhiyun reg = <0x0 0x8000000 0x0 0xF0000>; 155*4882a593Smuzhiyun record-size = <0x0 0x20000>; 156*4882a593Smuzhiyun console-size = <0x0 0x80000>; 157*4882a593Smuzhiyun ftrace-size = <0x0 0x00000>; 158*4882a593Smuzhiyun pmsg-size = <0x0 0x50000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 162*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 163*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun fiq-debugger { 168*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 169*4882a593Smuzhiyun interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 170*4882a593Smuzhiyun rockchip,serial-id = <2>; 171*4882a593Smuzhiyun rockchip,wake-irq = <0>; 172*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 173*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 174*4882a593Smuzhiyun rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 175*4882a593Smuzhiyun pinctrl-names = "default"; 176*4882a593Smuzhiyun pinctrl-0 = <&uart2_xfer>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun xin32k: xin32k { 180*4882a593Smuzhiyun compatible = "fixed-clock"; 181*4882a593Smuzhiyun clock-frequency = <32768>; 182*4882a593Smuzhiyun clock-output-names = "xin32k"; 183*4882a593Smuzhiyun #clock-cells = <0>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun vccadc_ref: vccadc-ref { 187*4882a593Smuzhiyun compatible = "regulator-fixed"; 188*4882a593Smuzhiyun regulator-name = "vcc1v8_sys"; 189*4882a593Smuzhiyun regulator-always-on; 190*4882a593Smuzhiyun regulator-boot-on; 191*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 192*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 198*4882a593Smuzhiyun compatible = "regulator-fixed"; 199*4882a593Smuzhiyun enable-active-high; 200*4882a593Smuzhiyun gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; 201*4882a593Smuzhiyun pinctrl-names = "default"; 202*4882a593Smuzhiyun pinctrl-0 = <ð_phy_pwr>; 203*4882a593Smuzhiyun regulator-name = "vcc_phy"; 204*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 205*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 206*4882a593Smuzhiyun regulator-always-on; 207*4882a593Smuzhiyun regulator-boot-on; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* 211*4882a593Smuzhiyun * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from 212*4882a593Smuzhiyun * vcc_io directly. Those boards won't be able to power cycle SD cards 213*4882a593Smuzhiyun * but it shouldn't hurt to toggle this pin there anyway. 214*4882a593Smuzhiyun */ 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun wireless-bluetooth { 217*4882a593Smuzhiyun clocks = <&hym8563>; 218*4882a593Smuzhiyun clock-names = "ext_clock"; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun rk_key: rockchip-key { 222*4882a593Smuzhiyun compatible = "rockchip,key"; 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun io-channels = <&saradc 1>; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun vol-up-key { 228*4882a593Smuzhiyun linux,code = <115>; 229*4882a593Smuzhiyun label = "volume up"; 230*4882a593Smuzhiyun rockchip,adc_value = <1>; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun vol-down-key { 234*4882a593Smuzhiyun linux,code = <114>; 235*4882a593Smuzhiyun label = "volume down"; 236*4882a593Smuzhiyun rockchip,adc_value = <170>; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun power-key { 240*4882a593Smuzhiyun gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 241*4882a593Smuzhiyun linux,code = <116>; 242*4882a593Smuzhiyun pinctrl-names = "default"; 243*4882a593Smuzhiyun pinctrl-0 = <&pwrbtn>; 244*4882a593Smuzhiyun label = "power"; 245*4882a593Smuzhiyun gpio-key,wakeup; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun menu-key { 249*4882a593Smuzhiyun linux,code = <59>; 250*4882a593Smuzhiyun label = "menu"; 251*4882a593Smuzhiyun rockchip,adc_value = <355>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun home-key { 255*4882a593Smuzhiyun linux,code = <102>; 256*4882a593Smuzhiyun label = "home"; 257*4882a593Smuzhiyun rockchip,adc_value = <746>; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun back-key { 261*4882a593Smuzhiyun linux,code = <158>; 262*4882a593Smuzhiyun label = "back"; 263*4882a593Smuzhiyun rockchip,adc_value = <560>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun camera-key { 267*4882a593Smuzhiyun linux,code = <212>; 268*4882a593Smuzhiyun label = "camera"; 269*4882a593Smuzhiyun rockchip,adc_value = <450>; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /delete-node/ usb-otg-regulator; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun}; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun&ir{ 278*4882a593Smuzhiyun /delete-property/ pinctrl-0; 279*4882a593Smuzhiyun}; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun&gmac { 282*4882a593Smuzhiyun phy-supply = <&vcc_phy>; 283*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 7 0>; 284*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 285*4882a593Smuzhiyun max-speed = <100>; 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun}; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun&saradc { 290*4882a593Smuzhiyun vref-supply = <&vccadc_ref>; 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&sdmmc { 295*4882a593Smuzhiyun sd-uhs-sdr12; 296*4882a593Smuzhiyun sd-uhs-sdr25; 297*4882a593Smuzhiyun sd-uhs-sdr50; 298*4882a593Smuzhiyun sd-uhs-sdr104; 299*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 300*4882a593Smuzhiyun status = "okay"; 301*4882a593Smuzhiyun}; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun&hdmi { 304*4882a593Smuzhiyun status = "okay"; 305*4882a593Smuzhiyun}; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun&edp { 308*4882a593Smuzhiyun force-hpd; 309*4882a593Smuzhiyun status = "okay"; 310*4882a593Smuzhiyun}; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun&edp_panel { 313*4882a593Smuzhiyun compatible ="lg,lp079qx1-sp0v", "simple-panel"; 314*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 315*4882a593Smuzhiyun bpc = <6>; 316*4882a593Smuzhiyun backlight = <&backlight>; 317*4882a593Smuzhiyun enable-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 318*4882a593Smuzhiyun reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 319*4882a593Smuzhiyun pinctrl-0 = <&lcd_cs>; 320*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 321*4882a593Smuzhiyun delay,prepare = <120>; 322*4882a593Smuzhiyun status = "okay"; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun disp_timings: display-timings { 325*4882a593Smuzhiyun native-mode = <&timing0>; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun timing0: timing0 { 328*4882a593Smuzhiyun clock-frequency = <205000000>; 329*4882a593Smuzhiyun hactive = <1536>; 330*4882a593Smuzhiyun vactive = <2048>; 331*4882a593Smuzhiyun hfront-porch = <12>; 332*4882a593Smuzhiyun hsync-len = <16>; 333*4882a593Smuzhiyun hback-porch = <48>; 334*4882a593Smuzhiyun vfront-porch = <8>; 335*4882a593Smuzhiyun vsync-len = <4>; 336*4882a593Smuzhiyun vback-porch = <8>; 337*4882a593Smuzhiyun hsync-active = <0>; 338*4882a593Smuzhiyun vsync-active = <0>; 339*4882a593Smuzhiyun de-active = <0>; 340*4882a593Smuzhiyun pixelclk-active = <0>; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun}; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun&route_edp { 346*4882a593Smuzhiyun status = "okay"; 347*4882a593Smuzhiyun}; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun&i2c0{ 350*4882a593Smuzhiyun /delete-node/ syr828@41; 351*4882a593Smuzhiyun /delete-node/ act8846@5a; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&i2c0 { 355*4882a593Smuzhiyun rk808: pmic@1b { 356*4882a593Smuzhiyun compatible = "rockchip,rk808"; 357*4882a593Smuzhiyun reg = <0x1b>; 358*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 359*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 360*4882a593Smuzhiyun pinctrl-names = "default"; 361*4882a593Smuzhiyun pinctrl-0 = <&pmic_int &global_pwroff>; 362*4882a593Smuzhiyun //pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; 363*4882a593Smuzhiyun rockchip,system-power-controller; 364*4882a593Smuzhiyun wakeup-source; 365*4882a593Smuzhiyun #clock-cells = <1>; 366*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 367*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 368*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 369*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 370*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 371*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 372*4882a593Smuzhiyun vcc7-supply = <&vcc_sys>; 373*4882a593Smuzhiyun vcc8-supply = <&vcc_18>; 374*4882a593Smuzhiyun vcc9-supply = <&vcc_io>; 375*4882a593Smuzhiyun vcc10-supply = <&vcc_io>; 376*4882a593Smuzhiyun vcc11-supply = <&vcc_sys>; 377*4882a593Smuzhiyun vcc12-supply = <&vcc_io>; 378*4882a593Smuzhiyun vddio-supply = <&vccio_pmu>; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun regulators { 381*4882a593Smuzhiyun rk808_dcdc1_reg: DCDC_REG1 { 382*4882a593Smuzhiyun regulator-always-on; 383*4882a593Smuzhiyun regulator-boot-on; 384*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 385*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 386*4882a593Smuzhiyun regulator-name = "vdd_arm"; 387*4882a593Smuzhiyun regulator-state-mem { 388*4882a593Smuzhiyun regulator-on-in-suspend; 389*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 394*4882a593Smuzhiyun regulator-always-on; 395*4882a593Smuzhiyun regulator-boot-on; 396*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 397*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 398*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 399*4882a593Smuzhiyun regulator-ramp-delay = <6000>; 400*4882a593Smuzhiyun regulator-state-mem { 401*4882a593Smuzhiyun regulator-on-in-suspend; 402*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 407*4882a593Smuzhiyun regulator-always-on; 408*4882a593Smuzhiyun regulator-boot-on; 409*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 410*4882a593Smuzhiyun regulator-state-mem { 411*4882a593Smuzhiyun regulator-on-in-suspend; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 416*4882a593Smuzhiyun regulator-always-on; 417*4882a593Smuzhiyun regulator-boot-on; 418*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 419*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 420*4882a593Smuzhiyun regulator-name = "vcc_io"; 421*4882a593Smuzhiyun regulator-state-mem { 422*4882a593Smuzhiyun regulator-on-in-suspend; 423*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun vccio_pmu: LDO_REG1 { 428*4882a593Smuzhiyun regulator-always-on; 429*4882a593Smuzhiyun regulator-boot-on; 430*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 431*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 432*4882a593Smuzhiyun regulator-name = "vccio_pmu"; 433*4882a593Smuzhiyun regulator-state-mem { 434*4882a593Smuzhiyun regulator-on-in-suspend; 435*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun vcca_33: LDO_REG2 { 440*4882a593Smuzhiyun regulator-always-on; 441*4882a593Smuzhiyun regulator-boot-on; 442*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 443*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 444*4882a593Smuzhiyun regulator-name = "vcca_33"; 445*4882a593Smuzhiyun regulator-state-mem { 446*4882a593Smuzhiyun regulator-off-in-suspend; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun vdd_10: LDO_REG3 { 451*4882a593Smuzhiyun regulator-always-on; 452*4882a593Smuzhiyun regulator-boot-on; 453*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 454*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 455*4882a593Smuzhiyun regulator-name = "vdd_10"; 456*4882a593Smuzhiyun regulator-state-mem { 457*4882a593Smuzhiyun regulator-on-in-suspend; 458*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun vcc18_lcd: LDO_REG4 { 463*4882a593Smuzhiyun regulator-always-on; 464*4882a593Smuzhiyun regulator-boot-on; 465*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 466*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 467*4882a593Smuzhiyun regulator-name = "vcc18_lcd"; 468*4882a593Smuzhiyun regulator-state-mem { 469*4882a593Smuzhiyun regulator-on-in-suspend; 470*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 475*4882a593Smuzhiyun regulator-always-on; 476*4882a593Smuzhiyun regulator-boot-on; 477*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 478*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 479*4882a593Smuzhiyun regulator-name = "vccio_sd"; 480*4882a593Smuzhiyun regulator-state-mem { 481*4882a593Smuzhiyun regulator-on-in-suspend; 482*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun vdd10_lcd: LDO_REG6 { 487*4882a593Smuzhiyun regulator-always-on; 488*4882a593Smuzhiyun regulator-boot-on; 489*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 490*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 491*4882a593Smuzhiyun regulator-name = "vdd10_lcd"; 492*4882a593Smuzhiyun regulator-state-mem { 493*4882a593Smuzhiyun regulator-on-in-suspend; 494*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun vcc_18: LDO_REG7 { 499*4882a593Smuzhiyun regulator-always-on; 500*4882a593Smuzhiyun regulator-boot-on; 501*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 502*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 503*4882a593Smuzhiyun regulator-name = "vcc_18"; 504*4882a593Smuzhiyun regulator-state-mem { 505*4882a593Smuzhiyun regulator-on-in-suspend; 506*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun vcc_lan: LDO_REG8 { 511*4882a593Smuzhiyun regulator-always-on; 512*4882a593Smuzhiyun regulator-boot-on; 513*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 514*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 515*4882a593Smuzhiyun regulator-name = "vcc_lan"; 516*4882a593Smuzhiyun regulator-state-mem { 517*4882a593Smuzhiyun regulator-on-in-suspend; 518*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun vccio_wl: SWITCH_REG1 { 523*4882a593Smuzhiyun regulator-always-on; 524*4882a593Smuzhiyun regulator-boot-on; 525*4882a593Smuzhiyun regulator-name = "vcc_18"; 526*4882a593Smuzhiyun regulator-state-mem { 527*4882a593Smuzhiyun regulator-on-in-suspend; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun rk808_ldo10_reg: SWITCH_REG2 { 532*4882a593Smuzhiyun regulator-always-on; 533*4882a593Smuzhiyun regulator-boot-on; 534*4882a593Smuzhiyun regulator-name = "rk_ldo10"; 535*4882a593Smuzhiyun regulator-state-mem { 536*4882a593Smuzhiyun regulator-on-in-suspend; 537*4882a593Smuzhiyun }; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun}; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun&i2c1 { 544*4882a593Smuzhiyun status = "okay"; 545*4882a593Smuzhiyun clock-frequency = <400000>; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun tc358749x: tc358749x@0f { 548*4882a593Smuzhiyun compatible = "toshiba,tc358749x"; 549*4882a593Smuzhiyun reg = <0x0f>; 550*4882a593Smuzhiyun power-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>; 551*4882a593Smuzhiyun stanby-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; 552*4882a593Smuzhiyun reset-gpios = <&gpio8 8 GPIO_ACTIVE_HIGH>; 553*4882a593Smuzhiyun int-gpios = <&gpio8 9 GPIO_ACTIVE_HIGH>; 554*4882a593Smuzhiyun pinctrl-names = "default"; 555*4882a593Smuzhiyun pinctrl-0 = <&hdmiin_gpios>; 556*4882a593Smuzhiyun status = "okay"; 557*4882a593Smuzhiyun }; 558*4882a593Smuzhiyun}; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun&i2c2 { 561*4882a593Smuzhiyun status = "okay"; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun es8323: es8323@10 { 564*4882a593Smuzhiyun status = "okay"; 565*4882a593Smuzhiyun compatible = "everest,es8323"; 566*4882a593Smuzhiyun reg = <0x10>; 567*4882a593Smuzhiyun spk-con-gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>; 568*4882a593Smuzhiyun hp-det-gpio = <&gpio7 15 GPIO_ACTIVE_LOW>; 569*4882a593Smuzhiyun clock-names = "mclk"; 570*4882a593Smuzhiyun clocks = <&cru SCLK_I2S0_OUT>; 571*4882a593Smuzhiyun pinctrl-names = "default"; 572*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 573*4882a593Smuzhiyun #sound-dai-cells = <0>; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun}; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun&i2c3 { 578*4882a593Smuzhiyun status = "okay"; 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&i2c4 { 582*4882a593Smuzhiyun status = "okay"; 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun gsl3680: gsl3680@40 { 585*4882a593Smuzhiyun status = "okay"; 586*4882a593Smuzhiyun compatible = "gslX680"; 587*4882a593Smuzhiyun reg = <0x40>; 588*4882a593Smuzhiyun screen_max_x = <1536>; 589*4882a593Smuzhiyun screen_max_y = <2048>; 590*4882a593Smuzhiyun flip-x = <1>; 591*4882a593Smuzhiyun flip-y = <1>; 592*4882a593Smuzhiyun touch-gpio = <&gpio7 13 IRQ_TYPE_EDGE_RISING>; 593*4882a593Smuzhiyun }; 594*4882a593Smuzhiyun}; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun&i2s { 597*4882a593Smuzhiyun #sound-dai-cells = <0>; 598*4882a593Smuzhiyun status = "okay"; 599*4882a593Smuzhiyun}; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun&pwm1 { 602*4882a593Smuzhiyun status = "okay"; 603*4882a593Smuzhiyun}; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun&isp { 606*4882a593Smuzhiyun /delete-property/ rockchip,gpios; 607*4882a593Smuzhiyun status = "okay"; 608*4882a593Smuzhiyun}; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun&isp_mmu { 611*4882a593Smuzhiyun status = "okay"; 612*4882a593Smuzhiyun}; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun&vpu_service { 615*4882a593Smuzhiyun status = "okay"; 616*4882a593Smuzhiyun}; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun&usb_host0_ehci { 619*4882a593Smuzhiyun rockchip-relinquish-port; 620*4882a593Smuzhiyun status = "okay"; 621*4882a593Smuzhiyun}; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun&vopb { 624*4882a593Smuzhiyun status = "okay"; 625*4882a593Smuzhiyun}; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun&vopl { 628*4882a593Smuzhiyun status = "okay"; 629*4882a593Smuzhiyun}; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun&dfi { 632*4882a593Smuzhiyun status = "okay"; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&dmac_bus_s { 636*4882a593Smuzhiyun /* change to non-secure dmac */ 637*4882a593Smuzhiyun reg = <0x0 0xff600000 0x0 0x4000>; 638*4882a593Smuzhiyun}; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun&dmc { 641*4882a593Smuzhiyun center-supply = <&vdd_gpu>; 642*4882a593Smuzhiyun status = "okay"; 643*4882a593Smuzhiyun}; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun&efuse { 646*4882a593Smuzhiyun compatible = "rockchip,rk3288-secure-efuse"; 647*4882a593Smuzhiyun}; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun&rga { 650*4882a593Smuzhiyun compatible = "rockchip,rga2"; 651*4882a593Smuzhiyun clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 652*4882a593Smuzhiyun clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 653*4882a593Smuzhiyun}; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun&rockchip_suspend { 656*4882a593Smuzhiyun status = "okay"; 657*4882a593Smuzhiyun}; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun&pwm0 { 660*4882a593Smuzhiyun status = "okay"; 661*4882a593Smuzhiyun interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 662*4882a593Smuzhiyun compatible = "rockchip,remotectl-pwm"; 663*4882a593Smuzhiyun remote_pwm_id = <0>; 664*4882a593Smuzhiyun handle_cpu_id = <0>; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun ir_key1{ 667*4882a593Smuzhiyun rockchip,usercode = <0xff00>; 668*4882a593Smuzhiyun rockchip,key_table = 669*4882a593Smuzhiyun <0xeb KEY_POWER>, 670*4882a593Smuzhiyun <0xec KEY_MENU>, 671*4882a593Smuzhiyun <0xfe KEY_BACK>, 672*4882a593Smuzhiyun <0xb7 KEY_HOME>, 673*4882a593Smuzhiyun <0xa3 KEY_WWW>, 674*4882a593Smuzhiyun <0xf4 KEY_VOLUMEUP>, 675*4882a593Smuzhiyun <0xa7 KEY_VOLUMEDOWN>, 676*4882a593Smuzhiyun <0xf8 KEY_REPLY>, 677*4882a593Smuzhiyun <0xfc KEY_UP>, 678*4882a593Smuzhiyun <0xfd KEY_DOWN>, 679*4882a593Smuzhiyun <0xf1 KEY_LEFT>, 680*4882a593Smuzhiyun <0xe5 KEY_RIGHT>; 681*4882a593Smuzhiyun }; 682*4882a593Smuzhiyun}; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun&tsadc { 685*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 686*4882a593Smuzhiyun}; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun&pinctrl { 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun /* sata:gpio0 c1 */ 691*4882a593Smuzhiyun init-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun pcfg_output_high: pcfg-output-high { 694*4882a593Smuzhiyun output-high; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun pcfg_output_low: pcfg-output-low { 698*4882a593Smuzhiyun output-low; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun pmic { 702*4882a593Smuzhiyun pmic_int: pmic-int { 703*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun eth_phy { 708*4882a593Smuzhiyun eth_phy_pwr: eth-phy-pwr { 709*4882a593Smuzhiyun rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun lcd { 714*4882a593Smuzhiyun lcd_cs: lcd-cs { 715*4882a593Smuzhiyun rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 716*4882a593Smuzhiyun }; 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun lcd_en: lcd-en { 719*4882a593Smuzhiyun rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 720*4882a593Smuzhiyun }; 721*4882a593Smuzhiyun }; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun act8846 { 724*4882a593Smuzhiyun pmic_vsel: pmic-vsel { 725*4882a593Smuzhiyun rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun pwr_hold: pwr-hold { 729*4882a593Smuzhiyun rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun backlight { 734*4882a593Smuzhiyun bl_en: bl-en { 735*4882a593Smuzhiyun rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 736*4882a593Smuzhiyun }; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun buttons { 740*4882a593Smuzhiyun pwrbtn: pwrbtn { 741*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun hdmiin { 746*4882a593Smuzhiyun hdmiin_gpios: hdmiin_gpios { 747*4882a593Smuzhiyun rockchip,pins = 748*4882a593Smuzhiyun <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 749*4882a593Smuzhiyun <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, 750*4882a593Smuzhiyun <8 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, 751*4882a593Smuzhiyun <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 752*4882a593Smuzhiyun }; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun}; 755