1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rk3288-firefly.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Firefly-RK3288 Beta"; 11*4882a593Smuzhiyun compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&ir { 15*4882a593Smuzhiyun gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&pinctrl { 19*4882a593Smuzhiyun act8846 { 20*4882a593Smuzhiyun pmic_vsel: pmic-vsel { 21*4882a593Smuzhiyun rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ir { 26*4882a593Smuzhiyun ir_int: ir-int { 27*4882a593Smuzhiyun rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&pwm0 { 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun}; 35