1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 3 4/dts-v1/; 5#include "rk3288-evb-rk628.dtsi" 6 7&sound { 8 status = "okay"; 9}; 10 11&rk628_hdmi { 12 status = "okay"; 13 14 ports { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 port@0 { 19 reg = <0>; 20 21 hdmi_in_post_process: endpoint { 22 remote-endpoint = <&post_process_out_hdmi>; 23 }; 24 }; 25 }; 26}; 27 28&rk628_post_process { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&rk628_vop_pins>; 31 status = "okay"; 32 33 ports { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 port@0 { 38 reg = <0>; 39 40 post_process_in_rgb: endpoint { 41 remote-endpoint = <&rgb_out_post_process>; 42 }; 43 }; 44 45 port@1 { 46 reg = <1>; 47 48 post_process_out_hdmi: endpoint { 49 remote-endpoint = <&hdmi_in_post_process>; 50 }; 51 }; 52 }; 53}; 54 55&rgb { 56 status = "okay"; 57 58 ports { 59 port@1 { 60 reg = <1>; 61 62 rgb_out_post_process: endpoint { 63 remote-endpoint = <&post_process_in_rgb>; 64 }; 65 }; 66 }; 67}; 68 69 70&video_phy { 71 status = "okay"; 72}; 73 74&rgb_in_vopb { 75 status = "disabled"; 76}; 77 78&rgb_in_vopl { 79 status = "okay"; 80}; 81 82&route_rgb { 83 connect = <&vopl_out_rgb>; 84 status = "disabled"; 85}; 86 87&vopb { 88 assigned-clocks = <&cru DCLK_VOP0>; 89 assigned-clock-parents = <&cru PLL_CPLL>; 90}; 91 92&vopl { 93 assigned-clocks = <&cru DCLK_VOP1>; 94 assigned-clock-parents = <&cru PLL_GPLL>; 95}; 96