1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 3*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 4*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 5*4882a593Smuzhiyun * whole. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 8*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 9*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 10*4882a593Smuzhiyun * License, or (at your option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 13*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4882a593Smuzhiyun * GNU General Public License for more details. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Or, alternatively, 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 20*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 21*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 22*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 23*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 24*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 25*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 26*4882a593Smuzhiyun * conditions: 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 29*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 33*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 35*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 36*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 37*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 38*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun/dts-v1/; 42*4882a593Smuzhiyun#include "rk3288-evb.dtsi" 43*4882a593Smuzhiyun#include "rk3288-android.dtsi" 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun/ { 46*4882a593Smuzhiyun compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun backlight: backlight { 49*4882a593Smuzhiyun compatible = "pwm-backlight"; 50*4882a593Smuzhiyun brightness-levels = < 51*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 52*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 53*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 54*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 55*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 56*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 57*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 58*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 59*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 60*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 61*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 62*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 63*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 64*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 65*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 66*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 67*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 68*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 69*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 70*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 71*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 72*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 73*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 74*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 75*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 76*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 77*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 78*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 79*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 80*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 81*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 82*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 83*4882a593Smuzhiyun default-brightness-level = <128>; 84*4882a593Smuzhiyun enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 85*4882a593Smuzhiyun pinctrl-names = "default"; 86*4882a593Smuzhiyun pinctrl-0 = <&bl_en>; 87*4882a593Smuzhiyun pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 91*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 92*4882a593Smuzhiyun clocks = <&hym8563>; 93*4882a593Smuzhiyun clock-names = "ext_clock"; 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * On the module itself this is one of these (depending 99*4882a593Smuzhiyun * on the actual card populated): 100*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 101*4882a593Smuzhiyun * - PDN (power down when low) 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun vcc_lcd: vcc-lcd { 107*4882a593Smuzhiyun compatible = "regulator-fixed"; 108*4882a593Smuzhiyun enable-active-high; 109*4882a593Smuzhiyun gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>; 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&lcd_en>; 112*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 113*4882a593Smuzhiyun vin-supply = <&vcc_io>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun vcc_wl: vcc-wl { 117*4882a593Smuzhiyun compatible = "regulator-fixed"; 118*4882a593Smuzhiyun enable-active-high; 119*4882a593Smuzhiyun gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; 120*4882a593Smuzhiyun pinctrl-names = "default"; 121*4882a593Smuzhiyun pinctrl-0 = <&wifi_pwr>; 122*4882a593Smuzhiyun regulator-name = "vcc_wl"; 123*4882a593Smuzhiyun vin-supply = <&vcc_18>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&cif_isp0 { 128*4882a593Smuzhiyun rockchip,camera-modules-attached = <&camera0>; 129*4882a593Smuzhiyun status = "disabled"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&cpu0 { 133*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&dfi { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&dmc { 141*4882a593Smuzhiyun center-supply = <&vdd_log>; 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&edp { 146*4882a593Smuzhiyun vcc-supply = <&vdd10_lcd>; 147*4882a593Smuzhiyun vccio-supply = <&vcc18_lcd>; 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&edp_panel { 152*4882a593Smuzhiyun compatible ="lg,lp079qx1-sp0v", "simple-panel"; 153*4882a593Smuzhiyun backlight = <&backlight>; 154*4882a593Smuzhiyun enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun enable-delay-ms = <120>; 156*4882a593Smuzhiyun pinctrl-0 = <&lcd_cs>; 157*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 158*4882a593Smuzhiyun status = "okay"; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun disp_timings: display-timings { 161*4882a593Smuzhiyun native-mode = <&timing0>; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun timing0: timing0 { 164*4882a593Smuzhiyun clock-frequency = <200000000>; 165*4882a593Smuzhiyun hactive = <1536>; 166*4882a593Smuzhiyun vactive = <2048>; 167*4882a593Smuzhiyun hfront-porch = <12>; 168*4882a593Smuzhiyun hsync-len = <16>; 169*4882a593Smuzhiyun hback-porch = <48>; 170*4882a593Smuzhiyun vfront-porch = <8>; 171*4882a593Smuzhiyun vsync-len = <4>; 172*4882a593Smuzhiyun vback-porch = <8>; 173*4882a593Smuzhiyun hsync-active = <0>; 174*4882a593Smuzhiyun vsync-active = <0>; 175*4882a593Smuzhiyun de-active = <0>; 176*4882a593Smuzhiyun pixelclk-active = <0>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun}; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun&gpu { 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&i2c0 { 187*4882a593Smuzhiyun clock-frequency = <400000>; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun vdd_cpu: syr827@40 { 190*4882a593Smuzhiyun compatible = "silergy,syr827"; 191*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 192*4882a593Smuzhiyun reg = <0x40>; 193*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 194*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 195*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 196*4882a593Smuzhiyun regulator-always-on; 197*4882a593Smuzhiyun regulator-boot-on; 198*4882a593Smuzhiyun regulator-enable-ramp-delay = <300>; 199*4882a593Smuzhiyun regulator-ramp-delay = <8000>; 200*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 201*4882a593Smuzhiyun regulator-state-mem { 202*4882a593Smuzhiyun regulator-off-in-suspend; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun vdd_gpu: syr828@41 { 207*4882a593Smuzhiyun compatible = "silergy,syr828"; 208*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 209*4882a593Smuzhiyun reg = <0x41>; 210*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 211*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 212*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 213*4882a593Smuzhiyun regulator-always-on; 214*4882a593Smuzhiyun regulator-ramp-delay = <6000>; 215*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 216*4882a593Smuzhiyun regulator-state-mem { 217*4882a593Smuzhiyun regulator-off-in-suspend; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun hym8563: hym8563@51 { 222*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 223*4882a593Smuzhiyun reg = <0x51>; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 226*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun pinctrl-names = "default"; 229*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #clock-cells = <0>; 232*4882a593Smuzhiyun clock-output-names = "xin32k"; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun act8846: act8846@5a { 236*4882a593Smuzhiyun compatible = "active-semi,act8846"; 237*4882a593Smuzhiyun reg = <0x5a>; 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun vp1-supply = <&vcc_sys>; 241*4882a593Smuzhiyun vp2-supply = <&vcc_sys>; 242*4882a593Smuzhiyun vp3-supply = <&vcc_sys>; 243*4882a593Smuzhiyun vp4-supply = <&vcc_sys>; 244*4882a593Smuzhiyun inl1-supply = <&vcc_io>; 245*4882a593Smuzhiyun inl2-supply = <&vcc_sys>; 246*4882a593Smuzhiyun inl3-supply = <&vcc_20>; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun regulators { 249*4882a593Smuzhiyun vcc_ddr: REG1 { 250*4882a593Smuzhiyun regulator-name = "VCC_DDR"; 251*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 252*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 253*4882a593Smuzhiyun regulator-always-on; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun vcc_io: REG2 { 257*4882a593Smuzhiyun regulator-name = "VCC_IO"; 258*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 259*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 260*4882a593Smuzhiyun regulator-always-on; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun vdd_log: REG3 { 264*4882a593Smuzhiyun regulator-name = "VDD_LOG"; 265*4882a593Smuzhiyun regulator-min-microvolt = <1150000>; 266*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 267*4882a593Smuzhiyun regulator-always-on; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun vcc_20: REG4 { 271*4882a593Smuzhiyun regulator-name = "VCC_20"; 272*4882a593Smuzhiyun regulator-min-microvolt = <2000000>; 273*4882a593Smuzhiyun regulator-max-microvolt = <2000000>; 274*4882a593Smuzhiyun regulator-always-on; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun vccio_sd: REG5 { 278*4882a593Smuzhiyun regulator-name = "VCCIO_SD"; 279*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 280*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 281*4882a593Smuzhiyun regulator-always-on; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun vdd10_lcd: REG6 { 285*4882a593Smuzhiyun regulator-name = "VDD10_LCD"; 286*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 287*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 288*4882a593Smuzhiyun regulator-always-on; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun vcca_codec: REG7 { 292*4882a593Smuzhiyun regulator-name = "VCCA_CODEC"; 293*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 294*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 295*4882a593Smuzhiyun regulator-always-on; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun vcca_tp: REG8 { 299*4882a593Smuzhiyun regulator-name = "VCCA_TP"; 300*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 301*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 302*4882a593Smuzhiyun regulator-always-on; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun vccio_pmu: REG9 { 306*4882a593Smuzhiyun regulator-name = "VCCIO_PMU"; 307*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 308*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 309*4882a593Smuzhiyun regulator-always-on; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun vdd_10: REG10 { 313*4882a593Smuzhiyun regulator-name = "VDD_10"; 314*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 315*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 316*4882a593Smuzhiyun regulator-always-on; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun vcc_18: REG11 { 320*4882a593Smuzhiyun regulator-name = "VCC_18"; 321*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 322*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 323*4882a593Smuzhiyun regulator-always-on; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun vcc18_lcd: REG12 { 327*4882a593Smuzhiyun regulator-name = "VCC18_LCD"; 328*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 329*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 330*4882a593Smuzhiyun regulator-always-on; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&i2c1 { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun clock-frequency = <400000>; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun mpu6050@68 { 341*4882a593Smuzhiyun compatible = "invensense,mpu6050"; 342*4882a593Smuzhiyun status = "okay"; 343*4882a593Smuzhiyun pinctrl-names = "default"; 344*4882a593Smuzhiyun pinctrl-0 = <&mpu6050_irq_gpio>; 345*4882a593Smuzhiyun reg = <0x68>; 346*4882a593Smuzhiyun irq-gpio = <&gpio8 0 IRQ_TYPE_EDGE_RISING>; 347*4882a593Smuzhiyun mpu-int_config = <0x10>; 348*4882a593Smuzhiyun mpu-level_shifter = <0>; 349*4882a593Smuzhiyun mpu-orientation = <0 1 0 1 0 0 0 0 1>; 350*4882a593Smuzhiyun orientation-x= <0>; 351*4882a593Smuzhiyun orientation-y= <1>; 352*4882a593Smuzhiyun orientation-z= <0>; 353*4882a593Smuzhiyun support-hw-poweroff = <1>; 354*4882a593Smuzhiyun mpu-debug = <1>; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun}; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun&i2c3 { 359*4882a593Smuzhiyun status = "okay"; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun camera0: camera-module@10 { 362*4882a593Smuzhiyun status = "disabled"; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun compatible = "omnivision,ov8858-v4l2-i2c-subdev"; 365*4882a593Smuzhiyun reg = <0x10>; 366*4882a593Smuzhiyun device_type = "v4l2-i2c-subdev"; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 369*4882a593Smuzhiyun clock-names = "clk_cif_out"; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default", 372*4882a593Smuzhiyun "rockchip,camera_sleep"; 373*4882a593Smuzhiyun pinctrl-0 = <&cam0_default_pins>; 374*4882a593Smuzhiyun pinctrl-1 = <&cam0_sleep_pins>; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun rockchip,pd-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>; 377*4882a593Smuzhiyun rockchip,pwr-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun rockchip,camera-module-mclk-name = "clk_cif_out"; 380*4882a593Smuzhiyun rockchip,camera-module-dovdd = "1.8v"; 381*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 382*4882a593Smuzhiyun rockchip,camera-module-name = "cmk-cb0695-fv1"; 383*4882a593Smuzhiyun rockchip,camera-module-len-name = "lg9569a2"; 384*4882a593Smuzhiyun rockchip,camera-module-fov-h = "66.0"; 385*4882a593Smuzhiyun rockchip,camera-module-fov-v = "50.1"; 386*4882a593Smuzhiyun rockchip,camera-module-orientation = <0>; 387*4882a593Smuzhiyun rockchip,camera-module-iq-flip = <0>; 388*4882a593Smuzhiyun rockchip,camera-module-iq-mirror = <0>; 389*4882a593Smuzhiyun rockchip,camera-module-flip = <0>; 390*4882a593Smuzhiyun rockchip,camera-module-mirror = <0>; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun /* resolution.w, resolution.h, defrect.left, defrect.top, defrect.w, defrect.h */ 393*4882a593Smuzhiyun rockchip,camera-module-defrect0 = <3264 2448 0 0 3264 2448>; 394*4882a593Smuzhiyun rockchip,camera-module-flash-support = <0>; 395*4882a593Smuzhiyun rockchip,camera-module-mipi-dphy-index = <0>; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun}; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun&i2c4 { 400*4882a593Smuzhiyun status = "okay"; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun ts@01 { 403*4882a593Smuzhiyun compatible = "ct,vtl_ts"; 404*4882a593Smuzhiyun reg = <0x01>; 405*4882a593Smuzhiyun screen_max_x = <1536>; 406*4882a593Smuzhiyun screen_max_y = <2048>; 407*4882a593Smuzhiyun xy_swap = <1>; 408*4882a593Smuzhiyun x_reverse = <0>; 409*4882a593Smuzhiyun y_reverse = <0>; 410*4882a593Smuzhiyun x_mul = <2>; 411*4882a593Smuzhiyun y_mul = <2>; 412*4882a593Smuzhiyun bin_ver = <0>; 413*4882a593Smuzhiyun irq_gpio_number = <&gpio7 6 IRQ_TYPE_LEVEL_LOW>; 414*4882a593Smuzhiyun rst_gpio_number = <&gpio7 5 GPIO_ACTIVE_HIGH>; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun}; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun&lvds_panel { 419*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 420*4882a593Smuzhiyun}; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun&rga { 423*4882a593Smuzhiyun status = "okay"; 424*4882a593Smuzhiyun}; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun&rockchip_suspend { 427*4882a593Smuzhiyun status = "okay"; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&route_edp { 431*4882a593Smuzhiyun status = "okay"; 432*4882a593Smuzhiyun}; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun&sound { 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun}; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun&uart2 { 439*4882a593Smuzhiyun status = "okay"; 440*4882a593Smuzhiyun}; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun&pinctrl { 443*4882a593Smuzhiyun backlight { 444*4882a593Smuzhiyun bl_en: bl-en { 445*4882a593Smuzhiyun rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun buttons { 450*4882a593Smuzhiyun pwrbtn: pwrbtn { 451*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun cam_pins { 456*4882a593Smuzhiyun cam0_default_pins: cam0-default-pins { 457*4882a593Smuzhiyun rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, 458*4882a593Smuzhiyun <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, 459*4882a593Smuzhiyun <2 RK_PB3 1 &pcfg_pull_none>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun cam0_sleep_pins: cam0-sleep-pins { 462*4882a593Smuzhiyun rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, 463*4882a593Smuzhiyun <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, 464*4882a593Smuzhiyun <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun lcd { 469*4882a593Smuzhiyun lcd_en: lcd-en { 470*4882a593Smuzhiyun rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun wifi { 475*4882a593Smuzhiyun wifi_pwr: wifi-pwr { 476*4882a593Smuzhiyun rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun mpu6050 { 481*4882a593Smuzhiyun mpu6050_irq_gpio: mpu6050-irq-gpio { 482*4882a593Smuzhiyun rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun}; 486