xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rk3288-dram-default-timing.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun * whole.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *  a) This library is free software; you can redistribute it and/or
10*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
12*4882a593Smuzhiyun *     License, or (at your option) any later version.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *     This library is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun *     GNU General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Or, alternatively,
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
22*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
23*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
24*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
25*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
26*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
27*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
28*4882a593Smuzhiyun *     conditions:
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
31*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun#include <dt-bindings/clock/rockchip-ddr.h>
43*4882a593Smuzhiyun#include <dt-bindings/memory/rk3288-dram.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun/ {
46*4882a593Smuzhiyun	ddr_timing: ddr_timing {
47*4882a593Smuzhiyun		compatible = "rockchip,ddr-timing";
48*4882a593Smuzhiyun		ddr3_speed_bin = <DDR3_DEFAULT>;
49*4882a593Smuzhiyun		pd_idle = <0x40>;
50*4882a593Smuzhiyun		sr_idle = <0x1>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		auto_pd_dis_freq = <800>;
53*4882a593Smuzhiyun		auto_sr_dis_freq = <800>;
54*4882a593Smuzhiyun		ddr3_dll_dis_freq = <300>;
55*4882a593Smuzhiyun		phy_dll_dis_freq = <250>;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		ddr3_odt_dis_freq = <333>;
58*4882a593Smuzhiyun		phy_ddr3_odt_dis_freq = <333>;
59*4882a593Smuzhiyun		ddr3_drv = <DDR3_DS_40ohm>;
60*4882a593Smuzhiyun		ddr3_odt = <DDR3_ODT_120ohm>;
61*4882a593Smuzhiyun		phy_ddr3_drv = <PHY_DDR3_RON_34ohm>;
62*4882a593Smuzhiyun		phy_ddr3_odt = <PHY_DDR3_RTT_155ohm>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		lpddr2_drv = <LP2_DS_40ohm>;
65*4882a593Smuzhiyun		phy_lpddr2_drv = <PHY_LP23_RON_35ohm>;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun		lpddr3_odt_dis_freq = <333>;
68*4882a593Smuzhiyun		phy_lpddr3_odt_dis_freq = <333>;
69*4882a593Smuzhiyun		lpddr3_drv = <LP3_DS_40ohm>;
70*4882a593Smuzhiyun		lpddr3_odt = <LP3_ODT_240ohm>;
71*4882a593Smuzhiyun		phy_lpddr3_drv = <PHY_LP23_RON_35ohm>;
72*4882a593Smuzhiyun		phy_lpddr3_odt = <PHY_LP23_RTT_155ohm>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75