1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/display/mipi_dsi.h> 7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 8*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun chosen: chosen { 12*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0x20068000"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpuinfo { 16*4882a593Smuzhiyun compatible = "rockchip,cpuinfo"; 17*4882a593Smuzhiyun nvmem-cells = <&efuse_id>; 18*4882a593Smuzhiyun nvmem-cell-names = "id"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun fiq-debugger { 22*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 23*4882a593Smuzhiyun rockchip,serial-id = <2>; 24*4882a593Smuzhiyun rockchip,signal-irq = <159>; 25*4882a593Smuzhiyun rockchip,wake-irq = <0>; 26*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 27*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 28*4882a593Smuzhiyun rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 29*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun firmware { 34*4882a593Smuzhiyun firmware_android: android {}; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun reserved-memory { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun ranges; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cma_region: region@63000000 { 43*4882a593Smuzhiyun compatible = "shared-dma-pool"; 44*4882a593Smuzhiyun reusable; 45*4882a593Smuzhiyun reg = <0x63000000 0x1800000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ramoops: ramoops@62e00000 { 49*4882a593Smuzhiyun compatible = "ramoops"; 50*4882a593Smuzhiyun reg = <0x62e00000 0xf0000>; 51*4882a593Smuzhiyun record-size = <0x20000>; 52*4882a593Smuzhiyun console-size = <0x80000>; 53*4882a593Smuzhiyun ftrace-size = <0x00000>; 54*4882a593Smuzhiyun pmsg-size = <0x50000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 58*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 59*4882a593Smuzhiyun reg = <0x0 0x0>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&cif_new { 65*4882a593Smuzhiyun memory-region = <&cma_region>; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&dfi { 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&display_subsystem { 73*4882a593Smuzhiyun memory-region = <&cma_region>; 74*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun route { 78*4882a593Smuzhiyun route_dsi: route-dsi { 79*4882a593Smuzhiyun status = "disabled"; 80*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 81*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 82*4882a593Smuzhiyun logo,mode = "center"; 83*4882a593Smuzhiyun charge_logo,mode = "center"; 84*4882a593Smuzhiyun connect = <&vop_out_dsi>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun route_lvds: route-lvds { 88*4882a593Smuzhiyun status = "disabled"; 89*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 90*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 91*4882a593Smuzhiyun logo,mode = "center"; 92*4882a593Smuzhiyun charge_logo,mode = "center"; 93*4882a593Smuzhiyun connect = <&vop_out_lvds>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun route_rgb: route-rgb { 97*4882a593Smuzhiyun status = "disabled"; 98*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 99*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 100*4882a593Smuzhiyun logo,mode = "center"; 101*4882a593Smuzhiyun charge_logo,mode = "center"; 102*4882a593Smuzhiyun connect = <&vop_out_rgb>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&dmc { 108*4882a593Smuzhiyun vop-dclk-mode = <1>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&dsi { 113*4882a593Smuzhiyun panel@0 { 114*4882a593Smuzhiyun reg = <0>; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun ports { 117*4882a593Smuzhiyun #address-cells = <1>; 118*4882a593Smuzhiyun #size-cells = <0>; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun port@0 { 121*4882a593Smuzhiyun reg = <0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun panel_in_dsi: endpoint { 124*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun ports { 131*4882a593Smuzhiyun #address-cells = <1>; 132*4882a593Smuzhiyun #size-cells = <0>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun port@1 { 135*4882a593Smuzhiyun reg = <1>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun dsi_out_panel: endpoint { 138*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&video_phy { 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun}; 147