1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rk3128h-box.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip RK3128h box avb board"; 12*4882a593Smuzhiyun compatible = "rockchip,rk3128h-box-avb", "rockchip,rk3128h"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&dmc_opp_table { 16*4882a593Smuzhiyun opp-300000000 { 17*4882a593Smuzhiyun status = "disabled"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun opp-330000000 { 20*4882a593Smuzhiyun status = "disabled"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun opp-666000000 { 23*4882a593Smuzhiyun status = "okay"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&dmc { 28*4882a593Smuzhiyun system-status-freq = < 29*4882a593Smuzhiyun /*system status freq(KHz)*/ 30*4882a593Smuzhiyun SYS_STATUS_NORMAL 666000 31*4882a593Smuzhiyun >; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&firmware_android { 35*4882a593Smuzhiyun compatible = "android,firmware"; 36*4882a593Smuzhiyun boot_devices = "30020000.dwmmc,30030000.nandc"; 37*4882a593Smuzhiyun vbmeta { 38*4882a593Smuzhiyun compatible = "android,vbmeta"; 39*4882a593Smuzhiyun parts = "vbmeta,boot,system,vendor,dtbo"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun fstab { 42*4882a593Smuzhiyun compatible = "android,fstab"; 43*4882a593Smuzhiyun vendor { 44*4882a593Smuzhiyun compatible = "android,vendor"; 45*4882a593Smuzhiyun dev = "/dev/block/by-name/vendor"; 46*4882a593Smuzhiyun type = "ext4"; 47*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 48*4882a593Smuzhiyun fsmgr_flags = "wait,avb"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&pinctrl { 54*4882a593Smuzhiyun sdmmc { 55*4882a593Smuzhiyun sdmmc_det: sdmmc-det { 56*4882a593Smuzhiyun rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&secure_memory { 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * enable like this: 64*4882a593Smuzhiyun * reg = <0x80000000 0x10000000>; 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun reg = <0x80000000 0x8000000>; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&sdmmc { 70*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_pwr &sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_det>; 71*4882a593Smuzhiyun}; 72