1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/dts-v1/; 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "rk3036.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "Rockchip RK3036 Evaluation board"; 9*4882a593Smuzhiyun compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun memory@60000000 { 12*4882a593Smuzhiyun device_type = "memory"; 13*4882a593Smuzhiyun reg = <0x60000000 0x40000000>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&emac { 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&emac_xfer>, <&emac_mdio>; 20*4882a593Smuzhiyun phy = <&phy0>; 21*4882a593Smuzhiyun phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ 22*4882a593Smuzhiyun phy-reset-duration = <10>; /* millisecond */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun phy0: ethernet-phy@0 { 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&i2c1 { 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun hym8563: rtc@51 { 35*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 36*4882a593Smuzhiyun reg = <0x51>; 37*4882a593Smuzhiyun #clock-cells = <0>; 38*4882a593Smuzhiyun clock-frequency = <32768>; 39*4882a593Smuzhiyun clock-output-names = "xin32k"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&uart2 { 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun}; 46