1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * RDA8810PL SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Andreas Färber 6*4882a593Smuzhiyun * Copyright (c) 2018 Manivannan Sadhasivam 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "rda,8810pl"; 13*4882a593Smuzhiyun interrupt-parent = <&intc>; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun device_type = "cpu"; 23*4882a593Smuzhiyun compatible = "arm,cortex-a5"; 24*4882a593Smuzhiyun reg = <0x0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun sram@100000 { 29*4882a593Smuzhiyun compatible = "mmio-sram"; 30*4882a593Smuzhiyun reg = <0x100000 0x10000>; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <1>; 33*4882a593Smuzhiyun ranges; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun modem@10000000 { 37*4882a593Smuzhiyun compatible = "simple-bus"; 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun ranges = <0x0 0x10000000 0xfffffff>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun gpioc@1a08000 { 43*4882a593Smuzhiyun compatible = "rda,8810pl-gpio"; 44*4882a593Smuzhiyun reg = <0x1a08000 0x1000>; 45*4882a593Smuzhiyun gpio-controller; 46*4882a593Smuzhiyun #gpio-cells = <2>; 47*4882a593Smuzhiyun ngpios = <32>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun apb@20800000 { 52*4882a593Smuzhiyun compatible = "simple-bus"; 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun ranges = <0x0 0x20800000 0x100000>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun intc: interrupt-controller@0 { 58*4882a593Smuzhiyun compatible = "rda,8810pl-intc"; 59*4882a593Smuzhiyun reg = <0x0 0x1000>; 60*4882a593Smuzhiyun interrupt-controller; 61*4882a593Smuzhiyun #interrupt-cells = <2>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun apb@20900000 { 66*4882a593Smuzhiyun compatible = "simple-bus"; 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <1>; 69*4882a593Smuzhiyun ranges = <0x0 0x20900000 0x100000>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun timer@10000 { 72*4882a593Smuzhiyun compatible = "rda,8810pl-timer"; 73*4882a593Smuzhiyun reg = <0x10000 0x1000>; 74*4882a593Smuzhiyun interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, 75*4882a593Smuzhiyun <17 IRQ_TYPE_LEVEL_HIGH>; 76*4882a593Smuzhiyun interrupt-names = "hwtimer", "ostimer"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun gpioa@30000 { 80*4882a593Smuzhiyun compatible = "rda,8810pl-gpio"; 81*4882a593Smuzhiyun reg = <0x30000 0x1000>; 82*4882a593Smuzhiyun gpio-controller; 83*4882a593Smuzhiyun #gpio-cells = <2>; 84*4882a593Smuzhiyun ngpios = <32>; 85*4882a593Smuzhiyun interrupt-controller; 86*4882a593Smuzhiyun #interrupt-cells = <2>; 87*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun gpiob@31000 { 91*4882a593Smuzhiyun compatible = "rda,8810pl-gpio"; 92*4882a593Smuzhiyun reg = <0x31000 0x1000>; 93*4882a593Smuzhiyun gpio-controller; 94*4882a593Smuzhiyun #gpio-cells = <2>; 95*4882a593Smuzhiyun ngpios = <32>; 96*4882a593Smuzhiyun interrupt-controller; 97*4882a593Smuzhiyun #interrupt-cells = <2>; 98*4882a593Smuzhiyun interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun gpiod@32000 { 102*4882a593Smuzhiyun compatible = "rda,8810pl-gpio"; 103*4882a593Smuzhiyun reg = <0x32000 0x1000>; 104*4882a593Smuzhiyun gpio-controller; 105*4882a593Smuzhiyun #gpio-cells = <2>; 106*4882a593Smuzhiyun ngpios = <32>; 107*4882a593Smuzhiyun interrupt-controller; 108*4882a593Smuzhiyun #interrupt-cells = <2>; 109*4882a593Smuzhiyun interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun apb@20a00000 { 114*4882a593Smuzhiyun compatible = "simple-bus"; 115*4882a593Smuzhiyun #address-cells = <1>; 116*4882a593Smuzhiyun #size-cells = <1>; 117*4882a593Smuzhiyun ranges = <0x0 0x20a00000 0x100000>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun uart1: serial@0 { 120*4882a593Smuzhiyun compatible = "rda,8810pl-uart"; 121*4882a593Smuzhiyun reg = <0x0 0x1000>; 122*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 123*4882a593Smuzhiyun status = "disabled"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun uart2: serial@10000 { 127*4882a593Smuzhiyun compatible = "rda,8810pl-uart"; 128*4882a593Smuzhiyun reg = <0x10000 0x1000>; 129*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 130*4882a593Smuzhiyun status = "disabled"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun uart3: serial@90000 { 134*4882a593Smuzhiyun compatible = "rda,8810pl-uart"; 135*4882a593Smuzhiyun reg = <0x90000 0x1000>; 136*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 137*4882a593Smuzhiyun status = "disabled"; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun l2: cache-controller@21100000 { 142*4882a593Smuzhiyun compatible = "arm,pl310-cache"; 143*4882a593Smuzhiyun reg = <0x21100000 0x1000>; 144*4882a593Smuzhiyun cache-unified; 145*4882a593Smuzhiyun cache-level = <2>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun}; 148