1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Andreas Färber 4*4882a593Smuzhiyun * Copyright (c) 2018 Manivannan Sadhasivam 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rda8810pl.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; 13*4882a593Smuzhiyun model = "Orange Pi 2G-IoT"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial0 = &uart1; 17*4882a593Smuzhiyun serial1 = &uart2; 18*4882a593Smuzhiyun serial2 = &uart3; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun chosen { 22*4882a593Smuzhiyun stdout-path = "serial2:921600n8"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun memory@80000000 { 26*4882a593Smuzhiyun device_type = "memory"; 27*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun uart_clk: uart-clk { 31*4882a593Smuzhiyun compatible = "fixed-clock"; 32*4882a593Smuzhiyun clock-frequency = <921600>; 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&uart1 { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun clocks = <&uart_clk>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&uart2 { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun clocks = <&uart_clk>; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&uart3 { 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun clocks = <&uart_clk>; 50*4882a593Smuzhiyun}; 51