xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r8a7793-gose.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Gose board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014-2015 Renesas Electronics Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/*
9*4882a593Smuzhiyun * SSI-AK4643
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SW1: 1: AK4643
12*4882a593Smuzhiyun *      2: CN22
13*4882a593Smuzhiyun *      3: ADV7511
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * This command is required when Playback/Capture
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun *	amixer set "LINEOUT Mixer DACL" on
18*4882a593Smuzhiyun *	amixer set "DVC Out" 100%
19*4882a593Smuzhiyun *	amixer set "DVC In" 100%
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * You can use Mute
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun *	amixer set "DVC Out Mute" on
24*4882a593Smuzhiyun *	amixer set "DVC In Mute" on
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * You can use Volume Ramp
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
29*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
30*4882a593Smuzhiyun *	amixer set "DVC Out Ramp" on
31*4882a593Smuzhiyun *	aplay xxx.wav &
32*4882a593Smuzhiyun *	amixer set "DVC Out"  80%  // Volume Down
33*4882a593Smuzhiyun *	amixer set "DVC Out" 100%  // Volume Up
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun/dts-v1/;
37*4882a593Smuzhiyun#include "r8a7793.dtsi"
38*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
39*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun/ {
42*4882a593Smuzhiyun	model = "Gose";
43*4882a593Smuzhiyun	compatible = "renesas,gose", "renesas,r8a7793";
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	aliases {
46*4882a593Smuzhiyun		serial0 = &scif0;
47*4882a593Smuzhiyun		serial1 = &scif1;
48*4882a593Smuzhiyun		i2c9 = &gpioi2c2;
49*4882a593Smuzhiyun		i2c10 = &gpioi2c4;
50*4882a593Smuzhiyun		i2c11 = &i2chdmi;
51*4882a593Smuzhiyun		i2c12 = &i2cexio4;
52*4882a593Smuzhiyun		mmc0 = &sdhi0;
53*4882a593Smuzhiyun		mmc1 = &sdhi1;
54*4882a593Smuzhiyun		mmc2 = &sdhi2;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	chosen {
58*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
59*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	memory@40000000 {
63*4882a593Smuzhiyun		device_type = "memory";
64*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	gpio-keys {
68*4882a593Smuzhiyun		compatible = "gpio-keys";
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		key-1 {
71*4882a593Smuzhiyun			gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
72*4882a593Smuzhiyun			linux,code = <KEY_1>;
73*4882a593Smuzhiyun			label = "SW2-1";
74*4882a593Smuzhiyun			wakeup-source;
75*4882a593Smuzhiyun			debounce-interval = <20>;
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun		key-2 {
78*4882a593Smuzhiyun			gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun			linux,code = <KEY_2>;
80*4882a593Smuzhiyun			label = "SW2-2";
81*4882a593Smuzhiyun			wakeup-source;
82*4882a593Smuzhiyun			debounce-interval = <20>;
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun		key-3 {
85*4882a593Smuzhiyun			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
86*4882a593Smuzhiyun			linux,code = <KEY_3>;
87*4882a593Smuzhiyun			label = "SW2-3";
88*4882a593Smuzhiyun			wakeup-source;
89*4882a593Smuzhiyun			debounce-interval = <20>;
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun		key-4 {
92*4882a593Smuzhiyun			gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
93*4882a593Smuzhiyun			linux,code = <KEY_4>;
94*4882a593Smuzhiyun			label = "SW2-4";
95*4882a593Smuzhiyun			wakeup-source;
96*4882a593Smuzhiyun			debounce-interval = <20>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun		key-a {
99*4882a593Smuzhiyun			gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
100*4882a593Smuzhiyun			linux,code = <KEY_A>;
101*4882a593Smuzhiyun			label = "SW30";
102*4882a593Smuzhiyun			wakeup-source;
103*4882a593Smuzhiyun			debounce-interval = <20>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun		key-b {
106*4882a593Smuzhiyun			gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
107*4882a593Smuzhiyun			linux,code = <KEY_B>;
108*4882a593Smuzhiyun			label = "SW31";
109*4882a593Smuzhiyun			wakeup-source;
110*4882a593Smuzhiyun			debounce-interval = <20>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun		key-c {
113*4882a593Smuzhiyun			gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
114*4882a593Smuzhiyun			linux,code = <KEY_C>;
115*4882a593Smuzhiyun			label = "SW32";
116*4882a593Smuzhiyun			wakeup-source;
117*4882a593Smuzhiyun			debounce-interval = <20>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun		key-d {
120*4882a593Smuzhiyun			gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
121*4882a593Smuzhiyun			linux,code = <KEY_D>;
122*4882a593Smuzhiyun			label = "SW33";
123*4882a593Smuzhiyun			wakeup-source;
124*4882a593Smuzhiyun			debounce-interval = <20>;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun		key-e {
127*4882a593Smuzhiyun			gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
128*4882a593Smuzhiyun			linux,code = <KEY_E>;
129*4882a593Smuzhiyun			label = "SW34";
130*4882a593Smuzhiyun			wakeup-source;
131*4882a593Smuzhiyun			debounce-interval = <20>;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun		key-f {
134*4882a593Smuzhiyun			gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
135*4882a593Smuzhiyun			linux,code = <KEY_F>;
136*4882a593Smuzhiyun			label = "SW35";
137*4882a593Smuzhiyun			wakeup-source;
138*4882a593Smuzhiyun			debounce-interval = <20>;
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun		key-g {
141*4882a593Smuzhiyun			gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
142*4882a593Smuzhiyun			linux,code = <KEY_G>;
143*4882a593Smuzhiyun			label = "SW36";
144*4882a593Smuzhiyun			wakeup-source;
145*4882a593Smuzhiyun			debounce-interval = <20>;
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	leds {
150*4882a593Smuzhiyun		compatible = "gpio-leds";
151*4882a593Smuzhiyun		led6 {
152*4882a593Smuzhiyun			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
153*4882a593Smuzhiyun			label = "LED6";
154*4882a593Smuzhiyun		};
155*4882a593Smuzhiyun		led7 {
156*4882a593Smuzhiyun			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun			label = "LED7";
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun		led8 {
160*4882a593Smuzhiyun			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
161*4882a593Smuzhiyun			label = "LED8";
162*4882a593Smuzhiyun		};
163*4882a593Smuzhiyun	};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
166*4882a593Smuzhiyun		compatible = "regulator-fixed";
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
169*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
170*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun		gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
173*4882a593Smuzhiyun		enable-active-high;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	vccq_sdhi0: regulator-vccq-sdhi0 {
177*4882a593Smuzhiyun		compatible = "regulator-gpio";
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun		regulator-name = "SDHI0 VccQ";
180*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
181*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
184*4882a593Smuzhiyun		gpios-states = <1>;
185*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	vcc_sdhi1: regulator-vcc-sdhi1 {
189*4882a593Smuzhiyun		compatible = "regulator-fixed";
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		regulator-name = "SDHI1 Vcc";
192*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
193*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
196*4882a593Smuzhiyun		enable-active-high;
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun	vccq_sdhi1: regulator-vccq-sdhi1 {
200*4882a593Smuzhiyun		compatible = "regulator-gpio";
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		regulator-name = "SDHI1 VccQ";
203*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
204*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
207*4882a593Smuzhiyun		gpios-states = <1>;
208*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	vcc_sdhi2: regulator-vcc-sdhi2 {
212*4882a593Smuzhiyun		compatible = "regulator-fixed";
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun		regulator-name = "SDHI2 Vcc";
215*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
216*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
219*4882a593Smuzhiyun		enable-active-high;
220*4882a593Smuzhiyun	};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	vccq_sdhi2: regulator-vccq-sdhi2 {
223*4882a593Smuzhiyun		compatible = "regulator-gpio";
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun		regulator-name = "SDHI2 VccQ";
226*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
227*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
230*4882a593Smuzhiyun		gpios-states = <1>;
231*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
232*4882a593Smuzhiyun	};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun	audio_clock: audio_clock {
235*4882a593Smuzhiyun		compatible = "fixed-clock";
236*4882a593Smuzhiyun		#clock-cells = <0>;
237*4882a593Smuzhiyun		clock-frequency = <11289600>;
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	rsnd_ak4643: sound {
241*4882a593Smuzhiyun		compatible = "simple-audio-card";
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun		simple-audio-card,format = "left_j";
244*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&sndcodec>;
245*4882a593Smuzhiyun		simple-audio-card,frame-master = <&sndcodec>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		sndcpu: simple-audio-card,cpu {
248*4882a593Smuzhiyun			sound-dai = <&rcar_sound>;
249*4882a593Smuzhiyun		};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun		sndcodec: simple-audio-card,codec {
252*4882a593Smuzhiyun			sound-dai = <&ak4643>;
253*4882a593Smuzhiyun			clocks = <&audio_clock>;
254*4882a593Smuzhiyun		};
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun	hdmi-in {
258*4882a593Smuzhiyun		compatible = "hdmi-connector";
259*4882a593Smuzhiyun		type = "a";
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun		port {
262*4882a593Smuzhiyun			hdmi_con_in: endpoint {
263*4882a593Smuzhiyun				remote-endpoint = <&adv7612_in>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun	hdmi-out {
269*4882a593Smuzhiyun		compatible = "hdmi-connector";
270*4882a593Smuzhiyun		type = "a";
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun		port {
273*4882a593Smuzhiyun			hdmi_con_out: endpoint {
274*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
275*4882a593Smuzhiyun			};
276*4882a593Smuzhiyun		};
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	composite-in {
280*4882a593Smuzhiyun		compatible = "composite-video-connector";
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun		port {
283*4882a593Smuzhiyun			composite_con_in: endpoint {
284*4882a593Smuzhiyun				remote-endpoint = <&adv7180_in>;
285*4882a593Smuzhiyun			};
286*4882a593Smuzhiyun		};
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	x2_clk: x2-clock {
290*4882a593Smuzhiyun		compatible = "fixed-clock";
291*4882a593Smuzhiyun		#clock-cells = <0>;
292*4882a593Smuzhiyun		clock-frequency = <74250000>;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	x13_clk: x13-clock {
296*4882a593Smuzhiyun		compatible = "fixed-clock";
297*4882a593Smuzhiyun		#clock-cells = <0>;
298*4882a593Smuzhiyun		clock-frequency = <148500000>;
299*4882a593Smuzhiyun	};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun	gpioi2c2: i2c-9 {
302*4882a593Smuzhiyun		#address-cells = <1>;
303*4882a593Smuzhiyun		#size-cells = <0>;
304*4882a593Smuzhiyun		compatible = "i2c-gpio";
305*4882a593Smuzhiyun		status = "disabled";
306*4882a593Smuzhiyun		scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
307*4882a593Smuzhiyun		sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
308*4882a593Smuzhiyun		i2c-gpio,delay-us = <5>;
309*4882a593Smuzhiyun	};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun	gpioi2c4: i2c-10 {
312*4882a593Smuzhiyun		#address-cells = <1>;
313*4882a593Smuzhiyun		#size-cells = <0>;
314*4882a593Smuzhiyun		compatible = "i2c-gpio";
315*4882a593Smuzhiyun		status = "disabled";
316*4882a593Smuzhiyun		scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
317*4882a593Smuzhiyun		sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
318*4882a593Smuzhiyun		i2c-gpio,delay-us = <5>;
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun	/*
322*4882a593Smuzhiyun	 * A fallback to GPIO is provided for I2C2.
323*4882a593Smuzhiyun	 */
324*4882a593Smuzhiyun	i2chdmi: i2c-11 {
325*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
326*4882a593Smuzhiyun		i2c-parent = <&i2c2>, <&gpioi2c2>;
327*4882a593Smuzhiyun		i2c-bus-name = "i2c-hdmi";
328*4882a593Smuzhiyun		#address-cells = <1>;
329*4882a593Smuzhiyun		#size-cells = <0>;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun		ak4643: codec@12 {
332*4882a593Smuzhiyun			compatible = "asahi-kasei,ak4643";
333*4882a593Smuzhiyun			#sound-dai-cells = <0>;
334*4882a593Smuzhiyun			reg = <0x12>;
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun		composite-in@20 {
338*4882a593Smuzhiyun			compatible = "adi,adv7180cp";
339*4882a593Smuzhiyun			reg = <0x20>;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun			ports {
342*4882a593Smuzhiyun				#address-cells = <1>;
343*4882a593Smuzhiyun				#size-cells = <0>;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun				port@0 {
346*4882a593Smuzhiyun					reg = <0>;
347*4882a593Smuzhiyun					adv7180_in: endpoint {
348*4882a593Smuzhiyun						remote-endpoint = <&composite_con_in>;
349*4882a593Smuzhiyun					};
350*4882a593Smuzhiyun				};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun				port@3 {
353*4882a593Smuzhiyun					reg = <3>;
354*4882a593Smuzhiyun					adv7180_out: endpoint {
355*4882a593Smuzhiyun						bus-width = <8>;
356*4882a593Smuzhiyun						remote-endpoint = <&vin1ep>;
357*4882a593Smuzhiyun					};
358*4882a593Smuzhiyun				};
359*4882a593Smuzhiyun			};
360*4882a593Smuzhiyun		};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun		hdmi@39 {
363*4882a593Smuzhiyun			compatible = "adi,adv7511w";
364*4882a593Smuzhiyun			reg = <0x39>;
365*4882a593Smuzhiyun			interrupt-parent = <&gpio3>;
366*4882a593Smuzhiyun			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun			adi,input-depth = <8>;
369*4882a593Smuzhiyun			adi,input-colorspace = "rgb";
370*4882a593Smuzhiyun			adi,input-clock = "1x";
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun			ports {
373*4882a593Smuzhiyun				#address-cells = <1>;
374*4882a593Smuzhiyun				#size-cells = <0>;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun				port@0 {
377*4882a593Smuzhiyun					reg = <0>;
378*4882a593Smuzhiyun					adv7511_in: endpoint {
379*4882a593Smuzhiyun						remote-endpoint = <&du_out_rgb>;
380*4882a593Smuzhiyun					};
381*4882a593Smuzhiyun				};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun				port@1 {
384*4882a593Smuzhiyun					reg = <1>;
385*4882a593Smuzhiyun					adv7511_out: endpoint {
386*4882a593Smuzhiyun						remote-endpoint = <&hdmi_con_out>;
387*4882a593Smuzhiyun					};
388*4882a593Smuzhiyun				};
389*4882a593Smuzhiyun			};
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun		hdmi-in@4c {
393*4882a593Smuzhiyun			compatible = "adi,adv7612";
394*4882a593Smuzhiyun			reg = <0x4c>;
395*4882a593Smuzhiyun			interrupt-parent = <&gpio4>;
396*4882a593Smuzhiyun			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
397*4882a593Smuzhiyun			default-input = <0>;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun			ports {
400*4882a593Smuzhiyun				#address-cells = <1>;
401*4882a593Smuzhiyun				#size-cells = <0>;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun				port@0 {
404*4882a593Smuzhiyun					reg = <0>;
405*4882a593Smuzhiyun					adv7612_in: endpoint {
406*4882a593Smuzhiyun						remote-endpoint = <&hdmi_con_in>;
407*4882a593Smuzhiyun					};
408*4882a593Smuzhiyun				};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun				port@2 {
411*4882a593Smuzhiyun					reg = <2>;
412*4882a593Smuzhiyun					adv7612_out: endpoint {
413*4882a593Smuzhiyun						remote-endpoint = <&vin0ep2>;
414*4882a593Smuzhiyun					};
415*4882a593Smuzhiyun				};
416*4882a593Smuzhiyun			};
417*4882a593Smuzhiyun		};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun		eeprom@50 {
420*4882a593Smuzhiyun			compatible = "renesas,r1ex24002", "atmel,24c02";
421*4882a593Smuzhiyun			reg = <0x50>;
422*4882a593Smuzhiyun			pagesize = <16>;
423*4882a593Smuzhiyun		};
424*4882a593Smuzhiyun	};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun	/*
427*4882a593Smuzhiyun	 * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
428*4882a593Smuzhiyun	 * A fallback to GPIO is provided.
429*4882a593Smuzhiyun	 */
430*4882a593Smuzhiyun	i2cexio4: i2c-12 {
431*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
432*4882a593Smuzhiyun		i2c-parent = <&i2c4>, <&gpioi2c4>;
433*4882a593Smuzhiyun		i2c-bus-name = "i2c-exio4";
434*4882a593Smuzhiyun		#address-cells = <1>;
435*4882a593Smuzhiyun		#size-cells = <0>;
436*4882a593Smuzhiyun	};
437*4882a593Smuzhiyun};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun&du {
440*4882a593Smuzhiyun	pinctrl-0 = <&du_pins>;
441*4882a593Smuzhiyun	pinctrl-names = "default";
442*4882a593Smuzhiyun	status = "okay";
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
445*4882a593Smuzhiyun		 <&x13_clk>, <&x2_clk>;
446*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	ports {
449*4882a593Smuzhiyun		port@0 {
450*4882a593Smuzhiyun			endpoint {
451*4882a593Smuzhiyun				remote-endpoint = <&adv7511_in>;
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun		};
454*4882a593Smuzhiyun	};
455*4882a593Smuzhiyun};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun&lvds0 {
458*4882a593Smuzhiyun	ports {
459*4882a593Smuzhiyun		port@1 {
460*4882a593Smuzhiyun			lvds_connector: endpoint {
461*4882a593Smuzhiyun			};
462*4882a593Smuzhiyun		};
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun&extal_clk {
467*4882a593Smuzhiyun	clock-frequency = <20000000>;
468*4882a593Smuzhiyun};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun&pfc {
471*4882a593Smuzhiyun	pinctrl-0 = <&scif_clk_pins>;
472*4882a593Smuzhiyun	pinctrl-names = "default";
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun	i2c2_pins: i2c2 {
475*4882a593Smuzhiyun		groups = "i2c2";
476*4882a593Smuzhiyun		function = "i2c2";
477*4882a593Smuzhiyun	};
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun	i2c4_pins: i2c4 {
480*4882a593Smuzhiyun		groups = "i2c4_c";
481*4882a593Smuzhiyun		function = "i2c4";
482*4882a593Smuzhiyun	};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun	du_pins: du {
485*4882a593Smuzhiyun		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
486*4882a593Smuzhiyun		function = "du";
487*4882a593Smuzhiyun	};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun	scif0_pins: scif0 {
490*4882a593Smuzhiyun		groups = "scif0_data_d";
491*4882a593Smuzhiyun		function = "scif0";
492*4882a593Smuzhiyun	};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun	scif1_pins: scif1 {
495*4882a593Smuzhiyun		groups = "scif1_data_d";
496*4882a593Smuzhiyun		function = "scif1";
497*4882a593Smuzhiyun	};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun	scif_clk_pins: scif_clk {
500*4882a593Smuzhiyun		groups = "scif_clk";
501*4882a593Smuzhiyun		function = "scif_clk";
502*4882a593Smuzhiyun	};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	ether_pins: ether {
505*4882a593Smuzhiyun		groups = "eth_link", "eth_mdio", "eth_rmii";
506*4882a593Smuzhiyun		function = "eth";
507*4882a593Smuzhiyun	};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun	phy1_pins: phy1 {
510*4882a593Smuzhiyun		groups = "intc_irq0";
511*4882a593Smuzhiyun		function = "intc";
512*4882a593Smuzhiyun	};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun	pmic_irq_pins: pmicirq {
515*4882a593Smuzhiyun		groups = "intc_irq2";
516*4882a593Smuzhiyun		function = "intc";
517*4882a593Smuzhiyun	};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun	sdhi0_pins: sd0 {
520*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
521*4882a593Smuzhiyun		function = "sdhi0";
522*4882a593Smuzhiyun		power-source = <3300>;
523*4882a593Smuzhiyun	};
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun	sdhi0_pins_uhs: sd0_uhs {
526*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
527*4882a593Smuzhiyun		function = "sdhi0";
528*4882a593Smuzhiyun		power-source = <1800>;
529*4882a593Smuzhiyun	};
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun	sdhi1_pins: sd1 {
532*4882a593Smuzhiyun		groups = "sdhi1_data4", "sdhi1_ctrl";
533*4882a593Smuzhiyun		function = "sdhi1";
534*4882a593Smuzhiyun		power-source = <3300>;
535*4882a593Smuzhiyun	};
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun	sdhi1_pins_uhs: sd1_uhs {
538*4882a593Smuzhiyun		groups = "sdhi1_data4", "sdhi1_ctrl";
539*4882a593Smuzhiyun		function = "sdhi1";
540*4882a593Smuzhiyun		power-source = <1800>;
541*4882a593Smuzhiyun	};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun	sdhi2_pins: sd2 {
544*4882a593Smuzhiyun		groups = "sdhi2_data4", "sdhi2_ctrl";
545*4882a593Smuzhiyun		function = "sdhi2";
546*4882a593Smuzhiyun		power-source = <3300>;
547*4882a593Smuzhiyun	};
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun	sdhi2_pins_uhs: sd2_uhs {
550*4882a593Smuzhiyun		groups = "sdhi2_data4", "sdhi2_ctrl";
551*4882a593Smuzhiyun		function = "sdhi2";
552*4882a593Smuzhiyun		power-source = <1800>;
553*4882a593Smuzhiyun	};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun	qspi_pins: qspi {
556*4882a593Smuzhiyun		groups = "qspi_ctrl", "qspi_data4";
557*4882a593Smuzhiyun		function = "qspi";
558*4882a593Smuzhiyun	};
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun	sound_pins: sound {
561*4882a593Smuzhiyun		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
562*4882a593Smuzhiyun		function = "ssi";
563*4882a593Smuzhiyun	};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun	sound_clk_pins: sound_clk {
566*4882a593Smuzhiyun		groups = "audio_clk_a";
567*4882a593Smuzhiyun		function = "audio_clk";
568*4882a593Smuzhiyun	};
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun	vin0_pins: vin0 {
571*4882a593Smuzhiyun		groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
572*4882a593Smuzhiyun		function = "vin0";
573*4882a593Smuzhiyun	};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun	vin1_pins: vin1 {
576*4882a593Smuzhiyun		groups = "vin1_data8", "vin1_clk";
577*4882a593Smuzhiyun		function = "vin1";
578*4882a593Smuzhiyun	};
579*4882a593Smuzhiyun};
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun&ether {
582*4882a593Smuzhiyun	pinctrl-0 = <&ether_pins &phy1_pins>;
583*4882a593Smuzhiyun	pinctrl-names = "default";
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun	phy-handle = <&phy1>;
586*4882a593Smuzhiyun	renesas,ether-link-active-low;
587*4882a593Smuzhiyun	status = "okay";
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun	phy1: ethernet-phy@1 {
590*4882a593Smuzhiyun		reg = <1>;
591*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
592*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
593*4882a593Smuzhiyun		micrel,led-mode = <1>;
594*4882a593Smuzhiyun		reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun&cmt0 {
599*4882a593Smuzhiyun	status = "okay";
600*4882a593Smuzhiyun};
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun&cpu0 {
603*4882a593Smuzhiyun	cpu0-supply = <&vdd_dvfs>;
604*4882a593Smuzhiyun};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun&rwdt {
607*4882a593Smuzhiyun	timeout-sec = <60>;
608*4882a593Smuzhiyun	status = "okay";
609*4882a593Smuzhiyun};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun&scif0 {
612*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
613*4882a593Smuzhiyun	pinctrl-names = "default";
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun	status = "okay";
616*4882a593Smuzhiyun};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun&scif1 {
619*4882a593Smuzhiyun	pinctrl-0 = <&scif1_pins>;
620*4882a593Smuzhiyun	pinctrl-names = "default";
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun	status = "okay";
623*4882a593Smuzhiyun};
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun&scif_clk {
626*4882a593Smuzhiyun	clock-frequency = <14745600>;
627*4882a593Smuzhiyun};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun&sdhi0 {
630*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
631*4882a593Smuzhiyun	pinctrl-1 = <&sdhi0_pins_uhs>;
632*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
635*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi0>;
636*4882a593Smuzhiyun	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
637*4882a593Smuzhiyun	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
638*4882a593Smuzhiyun	sd-uhs-sdr50;
639*4882a593Smuzhiyun	sd-uhs-sdr104;
640*4882a593Smuzhiyun	status = "okay";
641*4882a593Smuzhiyun};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun&sdhi1 {
644*4882a593Smuzhiyun	pinctrl-0 = <&sdhi1_pins>;
645*4882a593Smuzhiyun	pinctrl-1 = <&sdhi1_pins_uhs>;
646*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi1>;
649*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi1>;
650*4882a593Smuzhiyun	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
651*4882a593Smuzhiyun	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
652*4882a593Smuzhiyun	sd-uhs-sdr50;
653*4882a593Smuzhiyun	status = "okay";
654*4882a593Smuzhiyun};
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun&sdhi2 {
657*4882a593Smuzhiyun	pinctrl-0 = <&sdhi2_pins>;
658*4882a593Smuzhiyun	pinctrl-1 = <&sdhi2_pins_uhs>;
659*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi2>;
662*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi2>;
663*4882a593Smuzhiyun	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
664*4882a593Smuzhiyun	sd-uhs-sdr50;
665*4882a593Smuzhiyun	status = "okay";
666*4882a593Smuzhiyun};
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun&qspi {
669*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
670*4882a593Smuzhiyun	pinctrl-names = "default";
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun	status = "okay";
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun	flash@0 {
675*4882a593Smuzhiyun		compatible = "spansion,s25fl512s", "jedec,spi-nor";
676*4882a593Smuzhiyun		reg = <0>;
677*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
678*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
679*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
680*4882a593Smuzhiyun		spi-cpol;
681*4882a593Smuzhiyun		spi-cpha;
682*4882a593Smuzhiyun		m25p,fast-read;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun		partitions {
685*4882a593Smuzhiyun			compatible = "fixed-partitions";
686*4882a593Smuzhiyun			#address-cells = <1>;
687*4882a593Smuzhiyun			#size-cells = <1>;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun			partition@0 {
690*4882a593Smuzhiyun				label = "loader";
691*4882a593Smuzhiyun				reg = <0x00000000 0x00040000>;
692*4882a593Smuzhiyun				read-only;
693*4882a593Smuzhiyun			};
694*4882a593Smuzhiyun			partition@40000 {
695*4882a593Smuzhiyun				label = "user";
696*4882a593Smuzhiyun				reg = <0x00040000 0x00400000>;
697*4882a593Smuzhiyun				read-only;
698*4882a593Smuzhiyun			};
699*4882a593Smuzhiyun			partition@440000 {
700*4882a593Smuzhiyun				label = "flash";
701*4882a593Smuzhiyun				reg = <0x00440000 0x03bc0000>;
702*4882a593Smuzhiyun			};
703*4882a593Smuzhiyun		};
704*4882a593Smuzhiyun	};
705*4882a593Smuzhiyun};
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun&i2c2 {
708*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
709*4882a593Smuzhiyun	pinctrl-names = "i2c-hdmi";
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun	status = "okay";
712*4882a593Smuzhiyun	clock-frequency = <100000>;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun};
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun&i2c6 {
717*4882a593Smuzhiyun	pinctrl-names = "default";
718*4882a593Smuzhiyun	pinctrl-0 = <&pmic_irq_pins>;
719*4882a593Smuzhiyun	status = "okay";
720*4882a593Smuzhiyun	clock-frequency = <100000>;
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun	pmic@58 {
723*4882a593Smuzhiyun		compatible = "dlg,da9063";
724*4882a593Smuzhiyun		reg = <0x58>;
725*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
726*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
727*4882a593Smuzhiyun		interrupt-controller;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun		rtc {
730*4882a593Smuzhiyun			compatible = "dlg,da9063-rtc";
731*4882a593Smuzhiyun		};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun		wdt {
734*4882a593Smuzhiyun			compatible = "dlg,da9063-watchdog";
735*4882a593Smuzhiyun		};
736*4882a593Smuzhiyun	};
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun	vdd_dvfs: regulator@68 {
739*4882a593Smuzhiyun		compatible = "dlg,da9210";
740*4882a593Smuzhiyun		reg = <0x68>;
741*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
742*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun		regulator-min-microvolt = <1000000>;
745*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
746*4882a593Smuzhiyun		regulator-boot-on;
747*4882a593Smuzhiyun		regulator-always-on;
748*4882a593Smuzhiyun	};
749*4882a593Smuzhiyun};
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun&i2c4 {
752*4882a593Smuzhiyun	pinctrl-0 = <&i2c4_pins>;
753*4882a593Smuzhiyun	pinctrl-names = "i2c-exio4";
754*4882a593Smuzhiyun};
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun&rcar_sound {
757*4882a593Smuzhiyun	pinctrl-0 = <&sound_pins &sound_clk_pins>;
758*4882a593Smuzhiyun	pinctrl-names = "default";
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun	/* Single DAI */
761*4882a593Smuzhiyun	#sound-dai-cells = <0>;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun	status = "okay";
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun	rcar_sound,dai {
766*4882a593Smuzhiyun		dai0 {
767*4882a593Smuzhiyun			playback = <&ssi0 &src2 &dvc0>;
768*4882a593Smuzhiyun			capture  = <&ssi1 &src3 &dvc1>;
769*4882a593Smuzhiyun		};
770*4882a593Smuzhiyun	};
771*4882a593Smuzhiyun};
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun&ssi1 {
774*4882a593Smuzhiyun	shared-pin;
775*4882a593Smuzhiyun};
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun/* HDMI video input */
778*4882a593Smuzhiyun&vin0 {
779*4882a593Smuzhiyun	status = "okay";
780*4882a593Smuzhiyun	pinctrl-0 = <&vin0_pins>;
781*4882a593Smuzhiyun	pinctrl-names = "default";
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun	port {
784*4882a593Smuzhiyun		vin0ep2: endpoint {
785*4882a593Smuzhiyun			remote-endpoint = <&adv7612_out>;
786*4882a593Smuzhiyun			bus-width = <24>;
787*4882a593Smuzhiyun			hsync-active = <0>;
788*4882a593Smuzhiyun			vsync-active = <0>;
789*4882a593Smuzhiyun			pclk-sample = <1>;
790*4882a593Smuzhiyun			data-active = <1>;
791*4882a593Smuzhiyun		};
792*4882a593Smuzhiyun	};
793*4882a593Smuzhiyun};
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun/* composite video input */
796*4882a593Smuzhiyun&vin1 {
797*4882a593Smuzhiyun	pinctrl-0 = <&vin1_pins>;
798*4882a593Smuzhiyun	pinctrl-names = "default";
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun	status = "okay";
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun	port {
803*4882a593Smuzhiyun		vin1ep: endpoint {
804*4882a593Smuzhiyun			remote-endpoint = <&adv7180_out>;
805*4882a593Smuzhiyun			bus-width = <8>;
806*4882a593Smuzhiyun		};
807*4882a593Smuzhiyun	};
808*4882a593Smuzhiyun};
809