xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r8a7792-wheat.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Wheat board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corporation
6*4882a593Smuzhiyun * Copyright (C) 2016 Cogent  Embedded, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun#include "r8a7792.dtsi"
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Wheat";
16*4882a593Smuzhiyun	compatible = "renesas,wheat", "renesas,r8a7792";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	aliases {
19*4882a593Smuzhiyun		serial0 = &scif0;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
24*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	memory@40000000 {
28*4882a593Smuzhiyun		device_type = "memory";
29*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	d3_3v: regulator-3v3 {
33*4882a593Smuzhiyun		compatible = "regulator-fixed";
34*4882a593Smuzhiyun		regulator-name = "D3.3V";
35*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
36*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
37*4882a593Smuzhiyun		regulator-boot-on;
38*4882a593Smuzhiyun		regulator-always-on;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	ethernet@18000000 {
42*4882a593Smuzhiyun		compatible = "smsc,lan89218", "smsc,lan9115";
43*4882a593Smuzhiyun		reg = <0 0x18000000 0 0x100>;
44*4882a593Smuzhiyun		phy-mode = "mii";
45*4882a593Smuzhiyun		interrupt-parent = <&irqc>;
46*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
47*4882a593Smuzhiyun		smsc,irq-push-pull;
48*4882a593Smuzhiyun		smsc,save-mac-address;
49*4882a593Smuzhiyun		reg-io-width = <4>;
50*4882a593Smuzhiyun		vddvario-supply = <&d3_3v>;
51*4882a593Smuzhiyun		vdd33a-supply = <&d3_3v>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		pinctrl-0 = <&lan89218_pins>;
54*4882a593Smuzhiyun		pinctrl-names = "default";
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	keyboard {
58*4882a593Smuzhiyun		compatible = "gpio-keys";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		key-a {
61*4882a593Smuzhiyun			linux,code = <KEY_A>;
62*4882a593Smuzhiyun			label = "SW2";
63*4882a593Smuzhiyun			wakeup-source;
64*4882a593Smuzhiyun			debounce-interval = <20>;
65*4882a593Smuzhiyun			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun		key-b {
68*4882a593Smuzhiyun			linux,code = <KEY_B>;
69*4882a593Smuzhiyun			label = "SW3";
70*4882a593Smuzhiyun			wakeup-source;
71*4882a593Smuzhiyun			debounce-interval = <20>;
72*4882a593Smuzhiyun			gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
77*4882a593Smuzhiyun		compatible = "regulator-fixed";
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
80*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
81*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
84*4882a593Smuzhiyun		enable-active-high;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	hdmi-out0 {
88*4882a593Smuzhiyun		compatible = "hdmi-connector";
89*4882a593Smuzhiyun		type = "a";
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun		port {
92*4882a593Smuzhiyun			hdmi_con0: endpoint {
93*4882a593Smuzhiyun				remote-endpoint = <&adv7513_0_out>;
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	hdmi-out1 {
99*4882a593Smuzhiyun		compatible = "hdmi-connector";
100*4882a593Smuzhiyun		type = "a";
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		port {
103*4882a593Smuzhiyun			hdmi_con1: endpoint {
104*4882a593Smuzhiyun				remote-endpoint = <&adv7513_1_out>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	osc2_clk: osc2 {
110*4882a593Smuzhiyun		compatible = "fixed-clock";
111*4882a593Smuzhiyun		#clock-cells = <0>;
112*4882a593Smuzhiyun		clock-frequency = <74250000>;
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun&extal_clk {
117*4882a593Smuzhiyun	clock-frequency = <20000000>;
118*4882a593Smuzhiyun};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun&pfc {
121*4882a593Smuzhiyun	scif0_pins: scif0 {
122*4882a593Smuzhiyun		groups = "scif0_data";
123*4882a593Smuzhiyun		function = "scif0";
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	lan89218_pins: lan89218 {
127*4882a593Smuzhiyun		intc {
128*4882a593Smuzhiyun			groups = "intc_irq0";
129*4882a593Smuzhiyun			function = "intc";
130*4882a593Smuzhiyun		};
131*4882a593Smuzhiyun		lbsc {
132*4882a593Smuzhiyun			groups = "lbsc_ex_cs0";
133*4882a593Smuzhiyun			function = "lbsc";
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	can0_pins: can0 {
138*4882a593Smuzhiyun		groups = "can0_data";
139*4882a593Smuzhiyun		function = "can0";
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	can1_pins: can1 {
143*4882a593Smuzhiyun		groups = "can1_data";
144*4882a593Smuzhiyun		function = "can1";
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	sdhi0_pins: sdhi0 {
148*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
149*4882a593Smuzhiyun		function = "sdhi0";
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	qspi_pins: qspi {
153*4882a593Smuzhiyun		groups = "qspi_ctrl", "qspi_data4";
154*4882a593Smuzhiyun		function = "qspi";
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	du0_pins: du0 {
158*4882a593Smuzhiyun		groups = "du0_rgb888", "du0_sync", "du0_disp";
159*4882a593Smuzhiyun		function = "du0";
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	du1_pins: du1 {
163*4882a593Smuzhiyun		groups = "du1_rgb666", "du1_sync", "du1_disp";
164*4882a593Smuzhiyun		function = "du1";
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&rwdt {
169*4882a593Smuzhiyun	timeout-sec = <60>;
170*4882a593Smuzhiyun	status = "okay";
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun&scif0 {
174*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
175*4882a593Smuzhiyun	pinctrl-names = "default";
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	status = "okay";
178*4882a593Smuzhiyun};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun&can0 {
181*4882a593Smuzhiyun	pinctrl-0 = <&can0_pins>;
182*4882a593Smuzhiyun	pinctrl-names = "default";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	status = "okay";
185*4882a593Smuzhiyun};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun&can1 {
188*4882a593Smuzhiyun	pinctrl-0 = <&can1_pins>;
189*4882a593Smuzhiyun	pinctrl-names = "default";
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun&sdhi0 {
195*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
196*4882a593Smuzhiyun	pinctrl-names = "default";
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
199*4882a593Smuzhiyun	cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
200*4882a593Smuzhiyun	status = "okay";
201*4882a593Smuzhiyun};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun&qspi {
204*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
205*4882a593Smuzhiyun	pinctrl-names = "default";
206*4882a593Smuzhiyun	status = "okay";
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	flash@0 {
209*4882a593Smuzhiyun		compatible = "spansion,s25fl512s", "jedec,spi-nor";
210*4882a593Smuzhiyun		reg = <0>;
211*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
212*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
213*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
214*4882a593Smuzhiyun		spi-cpol;
215*4882a593Smuzhiyun		spi-cpha;
216*4882a593Smuzhiyun		m25p,fast-read;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		partitions {
219*4882a593Smuzhiyun			compatible = "fixed-partitions";
220*4882a593Smuzhiyun			#address-cells = <1>;
221*4882a593Smuzhiyun			#size-cells = <1>;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			partition@0 {
224*4882a593Smuzhiyun				label = "loader";
225*4882a593Smuzhiyun				reg = <0x00000000 0x00040000>;
226*4882a593Smuzhiyun				read-only;
227*4882a593Smuzhiyun			};
228*4882a593Smuzhiyun			partition@40000 {
229*4882a593Smuzhiyun				label = "user";
230*4882a593Smuzhiyun				reg = <0x00040000 0x00400000>;
231*4882a593Smuzhiyun				read-only;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun			partition@440000 {
234*4882a593Smuzhiyun				label = "flash";
235*4882a593Smuzhiyun				reg = <0x00440000 0x03bc0000>;
236*4882a593Smuzhiyun			};
237*4882a593Smuzhiyun		};
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&i2c4 {
242*4882a593Smuzhiyun	status = "okay";
243*4882a593Smuzhiyun	clock-frequency = <400000>;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun	/*
246*4882a593Smuzhiyun	 * The adv75xx resets its addresses to defaults during low power mode.
247*4882a593Smuzhiyun	 * Because we have two ADV7513 devices on the same bus, we must change
248*4882a593Smuzhiyun	 * both of them away from the defaults so that they do not conflict.
249*4882a593Smuzhiyun	 */
250*4882a593Smuzhiyun	hdmi@3d {
251*4882a593Smuzhiyun		compatible = "adi,adv7513";
252*4882a593Smuzhiyun		reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
253*4882a593Smuzhiyun		reg-names = "main", "edid", "cec", "packet";
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		adi,input-depth = <8>;
256*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
257*4882a593Smuzhiyun		adi,input-clock = "1x";
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun		ports {
260*4882a593Smuzhiyun			#address-cells = <1>;
261*4882a593Smuzhiyun			#size-cells = <0>;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun			port@0 {
264*4882a593Smuzhiyun				reg = <0>;
265*4882a593Smuzhiyun				adv7513_0_in: endpoint {
266*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb0>;
267*4882a593Smuzhiyun				};
268*4882a593Smuzhiyun			};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun			port@1 {
271*4882a593Smuzhiyun				reg = <1>;
272*4882a593Smuzhiyun				adv7513_0_out: endpoint {
273*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con0>;
274*4882a593Smuzhiyun				};
275*4882a593Smuzhiyun			};
276*4882a593Smuzhiyun		};
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	hdmi@39 {
280*4882a593Smuzhiyun		compatible = "adi,adv7513";
281*4882a593Smuzhiyun		reg = <0x39>, <0x49>, <0x29>, <0x59>;
282*4882a593Smuzhiyun		reg-names = "main", "edid", "cec", "packet";
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun		adi,input-depth = <8>;
285*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
286*4882a593Smuzhiyun		adi,input-clock = "1x";
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		ports {
289*4882a593Smuzhiyun			#address-cells = <1>;
290*4882a593Smuzhiyun			#size-cells = <0>;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun			port@0 {
293*4882a593Smuzhiyun				reg = <0>;
294*4882a593Smuzhiyun				adv7513_1_in: endpoint {
295*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb1>;
296*4882a593Smuzhiyun				};
297*4882a593Smuzhiyun			};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun			port@1 {
300*4882a593Smuzhiyun				reg = <1>;
301*4882a593Smuzhiyun				adv7513_1_out: endpoint {
302*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con1>;
303*4882a593Smuzhiyun				};
304*4882a593Smuzhiyun			};
305*4882a593Smuzhiyun		};
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun&du {
310*4882a593Smuzhiyun	pinctrl-0 = <&du0_pins &du1_pins>;
311*4882a593Smuzhiyun	pinctrl-names = "default";
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>;
314*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "dclkin.0";
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	ports {
318*4882a593Smuzhiyun		port@0 {
319*4882a593Smuzhiyun			endpoint {
320*4882a593Smuzhiyun				remote-endpoint = <&adv7513_0_in>;
321*4882a593Smuzhiyun			};
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun		port@1 {
324*4882a593Smuzhiyun			endpoint {
325*4882a593Smuzhiyun				remote-endpoint = <&adv7513_1_in>;
326*4882a593Smuzhiyun			};
327*4882a593Smuzhiyun		};
328*4882a593Smuzhiyun	};
329*4882a593Smuzhiyun};
330