xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r8a7790-stout.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Stout board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "r8a7790.dtsi"
10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	model = "Stout";
15*4882a593Smuzhiyun	compatible = "renesas,stout", "renesas,r8a7790";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	aliases {
18*4882a593Smuzhiyun		serial0 = &scifa0;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	chosen {
22*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
23*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	memory@40000000 {
27*4882a593Smuzhiyun		device_type = "memory";
28*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	leds {
32*4882a593Smuzhiyun		compatible = "gpio-leds";
33*4882a593Smuzhiyun		led1 {
34*4882a593Smuzhiyun			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
35*4882a593Smuzhiyun		};
36*4882a593Smuzhiyun		led2 {
37*4882a593Smuzhiyun			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun		led3 {
40*4882a593Smuzhiyun			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun		led5 {
43*4882a593Smuzhiyun			gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	fixedregulator3v3: regulator-3v3 {
48*4882a593Smuzhiyun		compatible = "regulator-fixed";
49*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
50*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
51*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
52*4882a593Smuzhiyun		regulator-boot-on;
53*4882a593Smuzhiyun		regulator-always-on;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
57*4882a593Smuzhiyun		compatible = "regulator-fixed";
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
60*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
61*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
64*4882a593Smuzhiyun		enable-active-high;
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	hdmi-out {
68*4882a593Smuzhiyun		compatible = "hdmi-connector";
69*4882a593Smuzhiyun		type = "a";
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		port {
72*4882a593Smuzhiyun			hdmi_con_out: endpoint {
73*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
74*4882a593Smuzhiyun			};
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun	};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun	osc1_clk: osc1-clock {
79*4882a593Smuzhiyun		compatible = "fixed-clock";
80*4882a593Smuzhiyun		#clock-cells = <0>;
81*4882a593Smuzhiyun		clock-frequency = <148500000>;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	osc4_clk: osc4-clock {
85*4882a593Smuzhiyun		compatible = "fixed-clock";
86*4882a593Smuzhiyun		#clock-cells = <0>;
87*4882a593Smuzhiyun		clock-frequency = <12000000>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&du {
92*4882a593Smuzhiyun	pinctrl-0 = <&du_pins>;
93*4882a593Smuzhiyun	pinctrl-names = "default";
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
97*4882a593Smuzhiyun		 <&osc1_clk>;
98*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "du.2", "dclkin.0";
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	ports {
101*4882a593Smuzhiyun		port@0 {
102*4882a593Smuzhiyun			endpoint {
103*4882a593Smuzhiyun				remote-endpoint = <&adv7511_in>;
104*4882a593Smuzhiyun			};
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&lvds0 {
110*4882a593Smuzhiyun	ports {
111*4882a593Smuzhiyun		port@1 {
112*4882a593Smuzhiyun			lvds_connector0: endpoint {
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&lvds1 {
119*4882a593Smuzhiyun	ports {
120*4882a593Smuzhiyun		port@1 {
121*4882a593Smuzhiyun			lvds_connector1: endpoint {
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun		};
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&extal_clk {
128*4882a593Smuzhiyun	clock-frequency = <20000000>;
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&pfc {
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	pinctrl-0 = <&scif_clk_pins>;
134*4882a593Smuzhiyun	pinctrl-names = "default";
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	du_pins: du {
137*4882a593Smuzhiyun		groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
138*4882a593Smuzhiyun		function = "du";
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	scifa0_pins: scifa0 {
142*4882a593Smuzhiyun		groups = "scifa0_data_b";
143*4882a593Smuzhiyun		function = "scifa0";
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	scif_clk_pins: scif_clk {
147*4882a593Smuzhiyun		groups = "scif_clk";
148*4882a593Smuzhiyun		function = "scif_clk";
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	ether_pins: ether {
152*4882a593Smuzhiyun		groups = "eth_link", "eth_mdio", "eth_rmii";
153*4882a593Smuzhiyun		function = "eth";
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun	phy1_pins: phy1 {
157*4882a593Smuzhiyun		groups = "intc_irq1";
158*4882a593Smuzhiyun		function = "intc";
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	sdhi0_pins: sd0 {
162*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
163*4882a593Smuzhiyun		function = "sdhi0";
164*4882a593Smuzhiyun		power-source = <3300>;
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	qspi_pins: qspi {
168*4882a593Smuzhiyun		groups = "qspi_ctrl", "qspi_data4";
169*4882a593Smuzhiyun		function = "qspi";
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	iic2_pins: iic2 {
173*4882a593Smuzhiyun		groups = "iic2_b";
174*4882a593Smuzhiyun		function = "iic2";
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	iic3_pins: iic3 {
178*4882a593Smuzhiyun		groups = "iic3";
179*4882a593Smuzhiyun		function = "iic3";
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	pmic_irq_pins: pmicirq {
183*4882a593Smuzhiyun		groups = "intc_irq2";
184*4882a593Smuzhiyun		function = "intc";
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun	usb0_pins: usb0 {
188*4882a593Smuzhiyun		groups = "usb0";
189*4882a593Smuzhiyun		function = "usb0";
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun&ether {
194*4882a593Smuzhiyun	pinctrl-0 = <&ether_pins &phy1_pins>;
195*4882a593Smuzhiyun	pinctrl-names = "default";
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	phy-handle = <&phy1>;
198*4882a593Smuzhiyun	renesas,ether-link-active-low;
199*4882a593Smuzhiyun	status = "okay";
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun	phy1: ethernet-phy@1 {
202*4882a593Smuzhiyun		reg = <1>;
203*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
204*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
205*4882a593Smuzhiyun		micrel,led-mode = <1>;
206*4882a593Smuzhiyun		reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
207*4882a593Smuzhiyun	};
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&cmt0 {
211*4882a593Smuzhiyun	status = "okay";
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&qspi {
215*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
216*4882a593Smuzhiyun	pinctrl-names = "default";
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	status = "okay";
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun	flash: flash@0 {
221*4882a593Smuzhiyun		compatible = "spansion,s25fl512s", "jedec,spi-nor";
222*4882a593Smuzhiyun		reg = <0>;
223*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
224*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
225*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
226*4882a593Smuzhiyun		spi-cpha;
227*4882a593Smuzhiyun		spi-cpol;
228*4882a593Smuzhiyun		m25p,fast-read;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun		partitions {
231*4882a593Smuzhiyun			compatible = "fixed-partitions";
232*4882a593Smuzhiyun			#address-cells = <1>;
233*4882a593Smuzhiyun			#size-cells = <1>;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun			partition@0 {
236*4882a593Smuzhiyun				label = "loader";
237*4882a593Smuzhiyun				reg = <0x00000000 0x00080000>;
238*4882a593Smuzhiyun				read-only;
239*4882a593Smuzhiyun			};
240*4882a593Smuzhiyun			partition@80000 {
241*4882a593Smuzhiyun				label = "uboot";
242*4882a593Smuzhiyun				reg = <0x00080000 0x00040000>;
243*4882a593Smuzhiyun				read-only;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun			partition@c0000 {
246*4882a593Smuzhiyun				label = "uboot-env";
247*4882a593Smuzhiyun				reg = <0x000c0000 0x00040000>;
248*4882a593Smuzhiyun				read-only;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun			partition@100000 {
251*4882a593Smuzhiyun				label = "flash";
252*4882a593Smuzhiyun				reg = <0x00100000 0x03f00000>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun		};
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&scifa0 {
259*4882a593Smuzhiyun	pinctrl-0 = <&scifa0_pins>;
260*4882a593Smuzhiyun	pinctrl-names = "default";
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	status = "okay";
263*4882a593Smuzhiyun};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun&scif_clk {
266*4882a593Smuzhiyun	clock-frequency = <14745600>;
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&sdhi0 {
270*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
274*4882a593Smuzhiyun	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
275*4882a593Smuzhiyun	status = "okay";
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun&cpu0 {
279*4882a593Smuzhiyun	cpu0-supply = <&vdd_dvfs>;
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&iic2	{
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun	pinctrl-0 = <&iic2_pins>;
285*4882a593Smuzhiyun	pinctrl-names = "default";
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	clock-frequency = <100000>;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	hdmi@39 {
290*4882a593Smuzhiyun		compatible = "adi,adv7511w";
291*4882a593Smuzhiyun		reg = <0x39>;
292*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
293*4882a593Smuzhiyun		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
294*4882a593Smuzhiyun		clocks = <&osc4_clk>;
295*4882a593Smuzhiyun		clock-names = "cec";
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun		adi,input-depth = <8>;
298*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
299*4882a593Smuzhiyun		adi,input-clock = "1x";
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun		ports {
302*4882a593Smuzhiyun			#address-cells = <1>;
303*4882a593Smuzhiyun			#size-cells = <0>;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun			port@0 {
306*4882a593Smuzhiyun				reg = <0>;
307*4882a593Smuzhiyun				adv7511_in: endpoint {
308*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb>;
309*4882a593Smuzhiyun				};
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun			port@1 {
313*4882a593Smuzhiyun				reg = <1>;
314*4882a593Smuzhiyun				adv7511_out: endpoint {
315*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con_out>;
316*4882a593Smuzhiyun				};
317*4882a593Smuzhiyun			};
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&iic3 {
323*4882a593Smuzhiyun	pinctrl-names = "default";
324*4882a593Smuzhiyun	pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
325*4882a593Smuzhiyun	status = "okay";
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun	pmic@58 {
328*4882a593Smuzhiyun		compatible = "dlg,da9063";
329*4882a593Smuzhiyun		reg = <0x58>;
330*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
331*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
332*4882a593Smuzhiyun		interrupt-controller;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun		onkey {
335*4882a593Smuzhiyun			compatible = "dlg,da9063-onkey";
336*4882a593Smuzhiyun		};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun		rtc {
339*4882a593Smuzhiyun			compatible = "dlg,da9063-rtc";
340*4882a593Smuzhiyun		};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun		wdt {
343*4882a593Smuzhiyun			compatible = "dlg,da9063-watchdog";
344*4882a593Smuzhiyun		};
345*4882a593Smuzhiyun	};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun	vdd_dvfs: regulator@68 {
348*4882a593Smuzhiyun		compatible = "dlg,da9210";
349*4882a593Smuzhiyun		reg = <0x68>;
350*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
351*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun		regulator-min-microvolt = <1000000>;
354*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
355*4882a593Smuzhiyun		regulator-boot-on;
356*4882a593Smuzhiyun		regulator-always-on;
357*4882a593Smuzhiyun	};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun	vdd: regulator@70 {
360*4882a593Smuzhiyun		compatible = "dlg,da9210";
361*4882a593Smuzhiyun		reg = <0x70>;
362*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
363*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun		regulator-min-microvolt = <1000000>;
366*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
367*4882a593Smuzhiyun		regulator-boot-on;
368*4882a593Smuzhiyun		regulator-always-on;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&pci0 {
373*4882a593Smuzhiyun	status = "okay";
374*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
375*4882a593Smuzhiyun	pinctrl-names = "default";
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&usbphy {
379*4882a593Smuzhiyun	status = "okay";
380*4882a593Smuzhiyun};
381