xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r8a7790-lager.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Lager board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2014 Renesas Solutions Corp.
6*4882a593Smuzhiyun * Copyright (C) 2014 Cogent Embedded, Inc.
7*4882a593Smuzhiyun * Copyright (C) 2015-2016 Renesas Electronics Corporation
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/*
11*4882a593Smuzhiyun * SSI-AK4643
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * SW1: 1: AK4643
14*4882a593Smuzhiyun *      2: CN22
15*4882a593Smuzhiyun *      3: ADV7511
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * This command is required when Playback/Capture
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun *	amixer set "LINEOUT Mixer DACL" on
20*4882a593Smuzhiyun *	amixer set "DVC Out" 100%
21*4882a593Smuzhiyun *	amixer set "DVC In" 100%
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * You can use Mute
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun *	amixer set "DVC Out Mute" on
26*4882a593Smuzhiyun *	amixer set "DVC In Mute" on
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * You can use Volume Ramp
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
31*4882a593Smuzhiyun *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32*4882a593Smuzhiyun *	amixer set "DVC Out Ramp" on
33*4882a593Smuzhiyun *	aplay xxx.wav &
34*4882a593Smuzhiyun *	amixer set "DVC Out"  80%  // Volume Down
35*4882a593Smuzhiyun *	amixer set "DVC Out" 100%  // Volume Up
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun/dts-v1/;
39*4882a593Smuzhiyun#include "r8a7790.dtsi"
40*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
41*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun/ {
44*4882a593Smuzhiyun	model = "Lager";
45*4882a593Smuzhiyun	compatible = "renesas,lager", "renesas,r8a7790";
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	aliases {
48*4882a593Smuzhiyun		serial0 = &scif0;
49*4882a593Smuzhiyun		serial1 = &scifa1;
50*4882a593Smuzhiyun		i2c8 = &gpioi2c1;
51*4882a593Smuzhiyun		i2c9 = &gpioi2c2;
52*4882a593Smuzhiyun		i2c10 = &i2cexio0;
53*4882a593Smuzhiyun		i2c11 = &i2cexio1;
54*4882a593Smuzhiyun		i2c12 = &i2chdmi;
55*4882a593Smuzhiyun		i2c13 = &i2cpwr;
56*4882a593Smuzhiyun		mmc0 = &mmcif1;
57*4882a593Smuzhiyun		mmc1 = &sdhi0;
58*4882a593Smuzhiyun		mmc2 = &sdhi2;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	chosen {
62*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
63*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	memory@40000000 {
67*4882a593Smuzhiyun		device_type = "memory";
68*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	memory@140000000 {
72*4882a593Smuzhiyun		device_type = "memory";
73*4882a593Smuzhiyun		reg = <1 0x40000000 0 0xc0000000>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	lbsc {
77*4882a593Smuzhiyun		#address-cells = <1>;
78*4882a593Smuzhiyun		#size-cells = <1>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	keyboard {
82*4882a593Smuzhiyun		compatible = "gpio-keys";
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		one {
85*4882a593Smuzhiyun			linux,code = <KEY_1>;
86*4882a593Smuzhiyun			label = "SW2-1";
87*4882a593Smuzhiyun			wakeup-source;
88*4882a593Smuzhiyun			debounce-interval = <20>;
89*4882a593Smuzhiyun			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun		two {
92*4882a593Smuzhiyun			linux,code = <KEY_2>;
93*4882a593Smuzhiyun			label = "SW2-2";
94*4882a593Smuzhiyun			wakeup-source;
95*4882a593Smuzhiyun			debounce-interval = <20>;
96*4882a593Smuzhiyun			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun		three {
99*4882a593Smuzhiyun			linux,code = <KEY_3>;
100*4882a593Smuzhiyun			label = "SW2-3";
101*4882a593Smuzhiyun			wakeup-source;
102*4882a593Smuzhiyun			debounce-interval = <20>;
103*4882a593Smuzhiyun			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun		four {
106*4882a593Smuzhiyun			linux,code = <KEY_4>;
107*4882a593Smuzhiyun			label = "SW2-4";
108*4882a593Smuzhiyun			wakeup-source;
109*4882a593Smuzhiyun			debounce-interval = <20>;
110*4882a593Smuzhiyun			gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	leds {
115*4882a593Smuzhiyun		compatible = "gpio-leds";
116*4882a593Smuzhiyun		led6 {
117*4882a593Smuzhiyun			gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun		led7 {
120*4882a593Smuzhiyun			gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun		led8 {
123*4882a593Smuzhiyun			gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	fixedregulator3v3: regulator-3v3 {
128*4882a593Smuzhiyun		compatible = "regulator-fixed";
129*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
130*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
131*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
132*4882a593Smuzhiyun		regulator-boot-on;
133*4882a593Smuzhiyun		regulator-always-on;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
137*4882a593Smuzhiyun		compatible = "regulator-fixed";
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
140*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
141*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
144*4882a593Smuzhiyun		enable-active-high;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	vccq_sdhi0: regulator-vccq-sdhi0 {
148*4882a593Smuzhiyun		compatible = "regulator-gpio";
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		regulator-name = "SDHI0 VccQ";
151*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
152*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
155*4882a593Smuzhiyun		gpios-states = <1>;
156*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	vcc_sdhi2: regulator-vcc-sdhi2 {
160*4882a593Smuzhiyun		compatible = "regulator-fixed";
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		regulator-name = "SDHI2 Vcc";
163*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
164*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
167*4882a593Smuzhiyun		enable-active-high;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	vccq_sdhi2: regulator-vccq-sdhi2 {
171*4882a593Smuzhiyun		compatible = "regulator-gpio";
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		regulator-name = "SDHI2 VccQ";
174*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
175*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun		gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
178*4882a593Smuzhiyun		gpios-states = <1>;
179*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	audio_clock: audio_clock {
183*4882a593Smuzhiyun		compatible = "fixed-clock";
184*4882a593Smuzhiyun		#clock-cells = <0>;
185*4882a593Smuzhiyun		clock-frequency = <11289600>;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	rsnd_ak4643: sound {
189*4882a593Smuzhiyun		compatible = "simple-audio-card";
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		simple-audio-card,format = "left_j";
192*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&sndcodec>;
193*4882a593Smuzhiyun		simple-audio-card,frame-master = <&sndcodec>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		sndcpu: simple-audio-card,cpu {
196*4882a593Smuzhiyun			sound-dai = <&rcar_sound>;
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		sndcodec: simple-audio-card,codec {
200*4882a593Smuzhiyun			sound-dai = <&ak4643>;
201*4882a593Smuzhiyun			clocks = <&audio_clock>;
202*4882a593Smuzhiyun		};
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	vga-encoder {
206*4882a593Smuzhiyun		compatible = "adi,adv7123";
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun		ports {
209*4882a593Smuzhiyun			#address-cells = <1>;
210*4882a593Smuzhiyun			#size-cells = <0>;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun			port@0 {
213*4882a593Smuzhiyun				reg = <0>;
214*4882a593Smuzhiyun				adv7123_in: endpoint {
215*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb>;
216*4882a593Smuzhiyun				};
217*4882a593Smuzhiyun			};
218*4882a593Smuzhiyun			port@1 {
219*4882a593Smuzhiyun				reg = <1>;
220*4882a593Smuzhiyun				adv7123_out: endpoint {
221*4882a593Smuzhiyun					remote-endpoint = <&vga_in>;
222*4882a593Smuzhiyun				};
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun		};
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	vga {
228*4882a593Smuzhiyun		compatible = "vga-connector";
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun		port {
231*4882a593Smuzhiyun			vga_in: endpoint {
232*4882a593Smuzhiyun				remote-endpoint = <&adv7123_out>;
233*4882a593Smuzhiyun			};
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun	};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	hdmi-in {
238*4882a593Smuzhiyun		compatible = "hdmi-connector";
239*4882a593Smuzhiyun		type = "a";
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		port {
242*4882a593Smuzhiyun			hdmi_con_in: endpoint {
243*4882a593Smuzhiyun				remote-endpoint = <&adv7612_in>;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun		};
246*4882a593Smuzhiyun	};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun	cec_clock: cec-clock {
249*4882a593Smuzhiyun		compatible = "fixed-clock";
250*4882a593Smuzhiyun		#clock-cells = <0>;
251*4882a593Smuzhiyun		clock-frequency = <12000000>;
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun	hdmi-out {
255*4882a593Smuzhiyun		compatible = "hdmi-connector";
256*4882a593Smuzhiyun		type = "a";
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun		port {
259*4882a593Smuzhiyun			hdmi_con_out: endpoint {
260*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
261*4882a593Smuzhiyun			};
262*4882a593Smuzhiyun		};
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	x2_clk: x2-clock {
266*4882a593Smuzhiyun		compatible = "fixed-clock";
267*4882a593Smuzhiyun		#clock-cells = <0>;
268*4882a593Smuzhiyun		clock-frequency = <148500000>;
269*4882a593Smuzhiyun	};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun	x13_clk: x13-clock {
272*4882a593Smuzhiyun		compatible = "fixed-clock";
273*4882a593Smuzhiyun		#clock-cells = <0>;
274*4882a593Smuzhiyun		clock-frequency = <148500000>;
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	gpioi2c1: i2c-8 {
278*4882a593Smuzhiyun		#address-cells = <1>;
279*4882a593Smuzhiyun		#size-cells = <0>;
280*4882a593Smuzhiyun		compatible = "i2c-gpio";
281*4882a593Smuzhiyun		status = "disabled";
282*4882a593Smuzhiyun		scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
283*4882a593Smuzhiyun		sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
284*4882a593Smuzhiyun		i2c-gpio,delay-us = <5>;
285*4882a593Smuzhiyun	};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	gpioi2c2: i2c-9 {
288*4882a593Smuzhiyun		#address-cells = <1>;
289*4882a593Smuzhiyun		#size-cells = <0>;
290*4882a593Smuzhiyun		compatible = "i2c-gpio";
291*4882a593Smuzhiyun		status = "disabled";
292*4882a593Smuzhiyun		scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
293*4882a593Smuzhiyun		sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
294*4882a593Smuzhiyun		i2c-gpio,delay-us = <5>;
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	/*
298*4882a593Smuzhiyun	 * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
299*4882a593Smuzhiyun	 * We use the I2C demuxer, so the desired IP core can be selected at runtime
300*4882a593Smuzhiyun	 * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
301*4882a593Smuzhiyun	 * Note: For testing the I2C slave feature, it is convenient to connect this
302*4882a593Smuzhiyun	 * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
303*4882a593Smuzhiyun	 * instantiate the slave device at runtime according to the documentation.
304*4882a593Smuzhiyun	 * You can then communicate with the slave via IIC3.
305*4882a593Smuzhiyun	 *
306*4882a593Smuzhiyun	 * IIC0/I2C0 does not appear to support fallback to GPIO.
307*4882a593Smuzhiyun	 */
308*4882a593Smuzhiyun	i2cexio0: i2c-10 {
309*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
310*4882a593Smuzhiyun		i2c-parent = <&iic0>, <&i2c0>;
311*4882a593Smuzhiyun		i2c-bus-name = "i2c-exio0";
312*4882a593Smuzhiyun		#address-cells = <1>;
313*4882a593Smuzhiyun		#size-cells = <0>;
314*4882a593Smuzhiyun	};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	/*
317*4882a593Smuzhiyun	 * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
318*4882a593Smuzhiyun	 * This is similar to the arangement described for i2cexio0 (above)
319*4882a593Smuzhiyun	 * with a fallback to GPIO also provided.
320*4882a593Smuzhiyun	 */
321*4882a593Smuzhiyun	i2cexio1: i2c-11 {
322*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
323*4882a593Smuzhiyun		i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
324*4882a593Smuzhiyun		i2c-bus-name = "i2c-exio1";
325*4882a593Smuzhiyun		#address-cells = <1>;
326*4882a593Smuzhiyun		#size-cells = <0>;
327*4882a593Smuzhiyun	};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	/*
330*4882a593Smuzhiyun	 * IIC2 and I2C2 may be switched using pinmux.
331*4882a593Smuzhiyun	 * A fallback to GPIO is also provided.
332*4882a593Smuzhiyun	 */
333*4882a593Smuzhiyun	i2chdmi: i2c-12 {
334*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
335*4882a593Smuzhiyun		i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
336*4882a593Smuzhiyun		i2c-bus-name = "i2c-hdmi";
337*4882a593Smuzhiyun		#address-cells = <1>;
338*4882a593Smuzhiyun		#size-cells = <0>;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun		ak4643: codec@12 {
341*4882a593Smuzhiyun			compatible = "asahi-kasei,ak4643";
342*4882a593Smuzhiyun			#sound-dai-cells = <0>;
343*4882a593Smuzhiyun			reg = <0x12>;
344*4882a593Smuzhiyun		};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun		composite-in@20 {
347*4882a593Smuzhiyun			compatible = "adi,adv7180";
348*4882a593Smuzhiyun			reg = <0x20>;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun			port {
351*4882a593Smuzhiyun				adv7180: endpoint {
352*4882a593Smuzhiyun					bus-width = <8>;
353*4882a593Smuzhiyun					remote-endpoint = <&vin1ep0>;
354*4882a593Smuzhiyun				};
355*4882a593Smuzhiyun			};
356*4882a593Smuzhiyun		};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun		hdmi@39 {
359*4882a593Smuzhiyun			compatible = "adi,adv7511w";
360*4882a593Smuzhiyun			reg = <0x39>;
361*4882a593Smuzhiyun			interrupt-parent = <&gpio1>;
362*4882a593Smuzhiyun			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
363*4882a593Smuzhiyun			clocks = <&cec_clock>;
364*4882a593Smuzhiyun			clock-names = "cec";
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun			adi,input-depth = <8>;
367*4882a593Smuzhiyun			adi,input-colorspace = "rgb";
368*4882a593Smuzhiyun			adi,input-clock = "1x";
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun			ports {
371*4882a593Smuzhiyun				#address-cells = <1>;
372*4882a593Smuzhiyun				#size-cells = <0>;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun				port@0 {
375*4882a593Smuzhiyun					reg = <0>;
376*4882a593Smuzhiyun					adv7511_in: endpoint {
377*4882a593Smuzhiyun						remote-endpoint = <&lvds0_out>;
378*4882a593Smuzhiyun					};
379*4882a593Smuzhiyun				};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun				port@1 {
382*4882a593Smuzhiyun					reg = <1>;
383*4882a593Smuzhiyun					adv7511_out: endpoint {
384*4882a593Smuzhiyun						remote-endpoint = <&hdmi_con_out>;
385*4882a593Smuzhiyun					};
386*4882a593Smuzhiyun				};
387*4882a593Smuzhiyun			};
388*4882a593Smuzhiyun		};
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun		hdmi-in@4c {
391*4882a593Smuzhiyun			compatible = "adi,adv7612";
392*4882a593Smuzhiyun			reg = <0x4c>;
393*4882a593Smuzhiyun			interrupt-parent = <&gpio1>;
394*4882a593Smuzhiyun			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
395*4882a593Smuzhiyun			default-input = <0>;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun			ports {
398*4882a593Smuzhiyun				#address-cells = <1>;
399*4882a593Smuzhiyun				#size-cells = <0>;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun				port@0 {
402*4882a593Smuzhiyun					reg = <0>;
403*4882a593Smuzhiyun					adv7612_in: endpoint {
404*4882a593Smuzhiyun						remote-endpoint = <&hdmi_con_in>;
405*4882a593Smuzhiyun					};
406*4882a593Smuzhiyun				};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun				port@2 {
409*4882a593Smuzhiyun					reg = <2>;
410*4882a593Smuzhiyun					adv7612_out: endpoint {
411*4882a593Smuzhiyun						remote-endpoint = <&vin0ep2>;
412*4882a593Smuzhiyun					};
413*4882a593Smuzhiyun				};
414*4882a593Smuzhiyun			};
415*4882a593Smuzhiyun		};
416*4882a593Smuzhiyun	};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun	/*
419*4882a593Smuzhiyun	 * IIC3 and I2C3 may be switched using pinmux.
420*4882a593Smuzhiyun	 * IIC3/I2C3 does not appear to support fallback to GPIO.
421*4882a593Smuzhiyun	 */
422*4882a593Smuzhiyun	i2cpwr: i2c-13 {
423*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
424*4882a593Smuzhiyun		pinctrl-names = "default";
425*4882a593Smuzhiyun		pinctrl-0 = <&pmic_irq_pins>;
426*4882a593Smuzhiyun		i2c-parent = <&iic3>, <&i2c3>;
427*4882a593Smuzhiyun		i2c-bus-name = "i2c-pwr";
428*4882a593Smuzhiyun		#address-cells = <1>;
429*4882a593Smuzhiyun		#size-cells = <0>;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun		pmic@58 {
432*4882a593Smuzhiyun			compatible = "dlg,da9063";
433*4882a593Smuzhiyun			reg = <0x58>;
434*4882a593Smuzhiyun			interrupt-parent = <&irqc0>;
435*4882a593Smuzhiyun			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
436*4882a593Smuzhiyun			interrupt-controller;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			rtc {
439*4882a593Smuzhiyun				compatible = "dlg,da9063-rtc";
440*4882a593Smuzhiyun			};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun			wdt {
443*4882a593Smuzhiyun				compatible = "dlg,da9063-watchdog";
444*4882a593Smuzhiyun			};
445*4882a593Smuzhiyun		};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun		vdd_dvfs: regulator@68 {
448*4882a593Smuzhiyun			compatible = "dlg,da9210";
449*4882a593Smuzhiyun			reg = <0x68>;
450*4882a593Smuzhiyun			interrupt-parent = <&irqc0>;
451*4882a593Smuzhiyun			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			regulator-min-microvolt = <1000000>;
454*4882a593Smuzhiyun			regulator-max-microvolt = <1000000>;
455*4882a593Smuzhiyun			regulator-boot-on;
456*4882a593Smuzhiyun			regulator-always-on;
457*4882a593Smuzhiyun		};
458*4882a593Smuzhiyun	};
459*4882a593Smuzhiyun};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun&du {
462*4882a593Smuzhiyun	pinctrl-0 = <&du_pins>;
463*4882a593Smuzhiyun	pinctrl-names = "default";
464*4882a593Smuzhiyun	status = "okay";
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
467*4882a593Smuzhiyun		 <&x13_clk>, <&x2_clk>;
468*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	ports {
471*4882a593Smuzhiyun		port@0 {
472*4882a593Smuzhiyun			endpoint {
473*4882a593Smuzhiyun				remote-endpoint = <&adv7123_in>;
474*4882a593Smuzhiyun			};
475*4882a593Smuzhiyun		};
476*4882a593Smuzhiyun	};
477*4882a593Smuzhiyun};
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun&lvds0 {
480*4882a593Smuzhiyun	status = "okay";
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	ports {
483*4882a593Smuzhiyun		port@1 {
484*4882a593Smuzhiyun			endpoint {
485*4882a593Smuzhiyun				remote-endpoint = <&adv7511_in>;
486*4882a593Smuzhiyun			};
487*4882a593Smuzhiyun		};
488*4882a593Smuzhiyun	};
489*4882a593Smuzhiyun};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun&lvds1 {
492*4882a593Smuzhiyun	ports {
493*4882a593Smuzhiyun		port@1 {
494*4882a593Smuzhiyun			lvds_connector: endpoint {
495*4882a593Smuzhiyun			};
496*4882a593Smuzhiyun		};
497*4882a593Smuzhiyun	};
498*4882a593Smuzhiyun};
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun&extal_clk {
501*4882a593Smuzhiyun	clock-frequency = <20000000>;
502*4882a593Smuzhiyun};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun&pfc {
505*4882a593Smuzhiyun	pinctrl-0 = <&scif_clk_pins>;
506*4882a593Smuzhiyun	pinctrl-names = "default";
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun	du_pins: du {
509*4882a593Smuzhiyun		groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
510*4882a593Smuzhiyun		function = "du";
511*4882a593Smuzhiyun	};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun	scif0_pins: scif0 {
514*4882a593Smuzhiyun		groups = "scif0_data";
515*4882a593Smuzhiyun		function = "scif0";
516*4882a593Smuzhiyun	};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun	scif_clk_pins: scif_clk {
519*4882a593Smuzhiyun		groups = "scif_clk";
520*4882a593Smuzhiyun		function = "scif_clk";
521*4882a593Smuzhiyun	};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun	ether_pins: ether {
524*4882a593Smuzhiyun		groups = "eth_link", "eth_mdio", "eth_rmii";
525*4882a593Smuzhiyun		function = "eth";
526*4882a593Smuzhiyun	};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun	phy1_pins: phy1 {
529*4882a593Smuzhiyun		groups = "intc_irq0";
530*4882a593Smuzhiyun		function = "intc";
531*4882a593Smuzhiyun	};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun	scifa1_pins: scifa1 {
534*4882a593Smuzhiyun		groups = "scifa1_data";
535*4882a593Smuzhiyun		function = "scifa1";
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	sdhi0_pins: sd0 {
539*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
540*4882a593Smuzhiyun		function = "sdhi0";
541*4882a593Smuzhiyun		power-source = <3300>;
542*4882a593Smuzhiyun	};
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun	sdhi0_pins_uhs: sd0_uhs {
545*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
546*4882a593Smuzhiyun		function = "sdhi0";
547*4882a593Smuzhiyun		power-source = <1800>;
548*4882a593Smuzhiyun	};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun	sdhi2_pins: sd2 {
551*4882a593Smuzhiyun		groups = "sdhi2_data4", "sdhi2_ctrl";
552*4882a593Smuzhiyun		function = "sdhi2";
553*4882a593Smuzhiyun		power-source = <3300>;
554*4882a593Smuzhiyun	};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun	sdhi2_pins_uhs: sd2_uhs {
557*4882a593Smuzhiyun		groups = "sdhi2_data4", "sdhi2_ctrl";
558*4882a593Smuzhiyun		function = "sdhi2";
559*4882a593Smuzhiyun		power-source = <1800>;
560*4882a593Smuzhiyun	};
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun	mmc1_pins: mmc1 {
563*4882a593Smuzhiyun		groups = "mmc1_data8", "mmc1_ctrl";
564*4882a593Smuzhiyun		function = "mmc1";
565*4882a593Smuzhiyun	};
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun	qspi_pins: qspi {
568*4882a593Smuzhiyun		groups = "qspi_ctrl", "qspi_data4";
569*4882a593Smuzhiyun		function = "qspi";
570*4882a593Smuzhiyun	};
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun	msiof1_pins: msiof1 {
573*4882a593Smuzhiyun		groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
574*4882a593Smuzhiyun				 "msiof1_tx";
575*4882a593Smuzhiyun		function = "msiof1";
576*4882a593Smuzhiyun	};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun	i2c0_pins: i2c0 {
579*4882a593Smuzhiyun		groups = "i2c0";
580*4882a593Smuzhiyun		function = "i2c0";
581*4882a593Smuzhiyun	};
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun	iic0_pins: iic0 {
584*4882a593Smuzhiyun		groups = "iic0";
585*4882a593Smuzhiyun		function = "iic0";
586*4882a593Smuzhiyun	};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun	i2c1_pins: i2c1 {
589*4882a593Smuzhiyun		groups = "i2c1";
590*4882a593Smuzhiyun		function = "i2c1";
591*4882a593Smuzhiyun	};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun	iic1_pins: iic1 {
594*4882a593Smuzhiyun		groups = "iic1";
595*4882a593Smuzhiyun		function = "iic1";
596*4882a593Smuzhiyun	};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun	i2c2_pins: i2c2 {
599*4882a593Smuzhiyun		groups = "i2c2";
600*4882a593Smuzhiyun		function = "i2c2";
601*4882a593Smuzhiyun	};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun	iic2_pins: iic2 {
604*4882a593Smuzhiyun		groups = "iic2";
605*4882a593Smuzhiyun		function = "iic2";
606*4882a593Smuzhiyun	};
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun	i2c3_pins: i2c3 {
609*4882a593Smuzhiyun		groups = "i2c3";
610*4882a593Smuzhiyun		function = "i2c3";
611*4882a593Smuzhiyun	};
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun	iic3_pins: iic3 {
614*4882a593Smuzhiyun		groups = "iic3";
615*4882a593Smuzhiyun		function = "iic3";
616*4882a593Smuzhiyun	};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun	pmic_irq_pins: pmicirq {
619*4882a593Smuzhiyun		groups = "intc_irq2";
620*4882a593Smuzhiyun		function = "intc";
621*4882a593Smuzhiyun	};
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun	hsusb_pins: hsusb {
624*4882a593Smuzhiyun		groups = "usb0_ovc_vbus";
625*4882a593Smuzhiyun		function = "usb0";
626*4882a593Smuzhiyun	};
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun	usb0_pins: usb0 {
629*4882a593Smuzhiyun		groups = "usb0";
630*4882a593Smuzhiyun		function = "usb0";
631*4882a593Smuzhiyun	};
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun	usb1_pins: usb1 {
634*4882a593Smuzhiyun		groups = "usb1";
635*4882a593Smuzhiyun		function = "usb1";
636*4882a593Smuzhiyun	};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun	usb2_pins: usb2 {
639*4882a593Smuzhiyun		groups = "usb2";
640*4882a593Smuzhiyun		function = "usb2";
641*4882a593Smuzhiyun	};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun	vin0_pins: vin0 {
644*4882a593Smuzhiyun		groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
645*4882a593Smuzhiyun		function = "vin0";
646*4882a593Smuzhiyun	};
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun	vin1_pins: vin1 {
649*4882a593Smuzhiyun		groups = "vin1_data8", "vin1_clk";
650*4882a593Smuzhiyun		function = "vin1";
651*4882a593Smuzhiyun	};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun	sound_pins: sound {
654*4882a593Smuzhiyun		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
655*4882a593Smuzhiyun		function = "ssi";
656*4882a593Smuzhiyun	};
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun	sound_clk_pins: sound_clk {
659*4882a593Smuzhiyun		groups = "audio_clk_a";
660*4882a593Smuzhiyun		function = "audio_clk";
661*4882a593Smuzhiyun	};
662*4882a593Smuzhiyun};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun&ether {
665*4882a593Smuzhiyun	pinctrl-0 = <&ether_pins &phy1_pins>;
666*4882a593Smuzhiyun	pinctrl-names = "default";
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun	phy-handle = <&phy1>;
669*4882a593Smuzhiyun	renesas,ether-link-active-low;
670*4882a593Smuzhiyun	status = "okay";
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun	phy1: ethernet-phy@1 {
673*4882a593Smuzhiyun		reg = <1>;
674*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
675*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
676*4882a593Smuzhiyun		micrel,led-mode = <1>;
677*4882a593Smuzhiyun		reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
678*4882a593Smuzhiyun	};
679*4882a593Smuzhiyun};
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun&cmt0 {
682*4882a593Smuzhiyun	status = "okay";
683*4882a593Smuzhiyun};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun&mmcif1 {
686*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
687*4882a593Smuzhiyun	pinctrl-names = "default";
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun	vmmc-supply = <&fixedregulator3v3>;
690*4882a593Smuzhiyun	bus-width = <8>;
691*4882a593Smuzhiyun	non-removable;
692*4882a593Smuzhiyun	status = "okay";
693*4882a593Smuzhiyun};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun&sata1 {
696*4882a593Smuzhiyun	status = "okay";
697*4882a593Smuzhiyun};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun&qspi {
700*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
701*4882a593Smuzhiyun	pinctrl-names = "default";
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun	status = "okay";
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun	flash: flash@0 {
706*4882a593Smuzhiyun		compatible = "spansion,s25fl512s", "jedec,spi-nor";
707*4882a593Smuzhiyun		reg = <0>;
708*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
709*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
710*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
711*4882a593Smuzhiyun		spi-cpha;
712*4882a593Smuzhiyun		spi-cpol;
713*4882a593Smuzhiyun		m25p,fast-read;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun		partitions {
716*4882a593Smuzhiyun			compatible = "fixed-partitions";
717*4882a593Smuzhiyun			#address-cells = <1>;
718*4882a593Smuzhiyun			#size-cells = <1>;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun			partition@0 {
721*4882a593Smuzhiyun				label = "loader";
722*4882a593Smuzhiyun				reg = <0x00000000 0x00040000>;
723*4882a593Smuzhiyun				read-only;
724*4882a593Smuzhiyun			};
725*4882a593Smuzhiyun			partition@40000 {
726*4882a593Smuzhiyun				label = "user";
727*4882a593Smuzhiyun				reg = <0x00040000 0x00400000>;
728*4882a593Smuzhiyun				read-only;
729*4882a593Smuzhiyun			};
730*4882a593Smuzhiyun			partition@440000 {
731*4882a593Smuzhiyun				label = "flash";
732*4882a593Smuzhiyun				reg = <0x00440000 0x03bc0000>;
733*4882a593Smuzhiyun			};
734*4882a593Smuzhiyun		};
735*4882a593Smuzhiyun	};
736*4882a593Smuzhiyun};
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun&scif0 {
739*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
740*4882a593Smuzhiyun	pinctrl-names = "default";
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun	status = "okay";
743*4882a593Smuzhiyun};
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun&scifa1 {
746*4882a593Smuzhiyun	pinctrl-0 = <&scifa1_pins>;
747*4882a593Smuzhiyun	pinctrl-names = "default";
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun	status = "okay";
750*4882a593Smuzhiyun};
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun&scif_clk {
753*4882a593Smuzhiyun	clock-frequency = <14745600>;
754*4882a593Smuzhiyun};
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun&msiof1 {
757*4882a593Smuzhiyun	pinctrl-0 = <&msiof1_pins>;
758*4882a593Smuzhiyun	pinctrl-names = "default";
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun	status = "okay";
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun	pmic: pmic@0 {
763*4882a593Smuzhiyun		compatible = "renesas,r2a11302ft";
764*4882a593Smuzhiyun		reg = <0>;
765*4882a593Smuzhiyun		spi-max-frequency = <6000000>;
766*4882a593Smuzhiyun		spi-cpol;
767*4882a593Smuzhiyun		spi-cpha;
768*4882a593Smuzhiyun	};
769*4882a593Smuzhiyun};
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun&sdhi0 {
772*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
773*4882a593Smuzhiyun	pinctrl-1 = <&sdhi0_pins_uhs>;
774*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
777*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi0>;
778*4882a593Smuzhiyun	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
779*4882a593Smuzhiyun	sd-uhs-sdr50;
780*4882a593Smuzhiyun	sd-uhs-sdr104;
781*4882a593Smuzhiyun	status = "okay";
782*4882a593Smuzhiyun};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun&sdhi2 {
785*4882a593Smuzhiyun	pinctrl-0 = <&sdhi2_pins>;
786*4882a593Smuzhiyun	pinctrl-1 = <&sdhi2_pins_uhs>;
787*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi2>;
790*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi2>;
791*4882a593Smuzhiyun	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
792*4882a593Smuzhiyun	sd-uhs-sdr50;
793*4882a593Smuzhiyun	status = "okay";
794*4882a593Smuzhiyun};
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun&cpu0 {
797*4882a593Smuzhiyun	cpu0-supply = <&vdd_dvfs>;
798*4882a593Smuzhiyun};
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun&i2c0	{
801*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
802*4882a593Smuzhiyun	pinctrl-names = "i2c-exio0";
803*4882a593Smuzhiyun};
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun&iic0	{
806*4882a593Smuzhiyun	pinctrl-0 = <&iic0_pins>;
807*4882a593Smuzhiyun	pinctrl-names = "i2c-exio0";
808*4882a593Smuzhiyun};
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun&i2c1	{
811*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
812*4882a593Smuzhiyun	pinctrl-names = "i2c-exio1";
813*4882a593Smuzhiyun};
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun&iic1	{
816*4882a593Smuzhiyun	pinctrl-0 = <&iic1_pins>;
817*4882a593Smuzhiyun	pinctrl-names = "i2c-exio1";
818*4882a593Smuzhiyun};
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun&i2c2	{
821*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
822*4882a593Smuzhiyun	pinctrl-names = "i2c-hdmi";
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun	clock-frequency = <100000>;
825*4882a593Smuzhiyun};
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun&iic2	{
828*4882a593Smuzhiyun	pinctrl-0 = <&iic2_pins>;
829*4882a593Smuzhiyun	pinctrl-names = "i2c-hdmi";
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun	clock-frequency = <100000>;
832*4882a593Smuzhiyun};
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun&i2c3	{
835*4882a593Smuzhiyun	pinctrl-0 = <&i2c3_pins>;
836*4882a593Smuzhiyun	pinctrl-names = "i2c-pwr";
837*4882a593Smuzhiyun};
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun&iic3	{
840*4882a593Smuzhiyun	pinctrl-0 = <&iic3_pins>;
841*4882a593Smuzhiyun	pinctrl-names = "i2c-pwr";
842*4882a593Smuzhiyun};
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun&pci0 {
845*4882a593Smuzhiyun	status = "okay";
846*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
847*4882a593Smuzhiyun	pinctrl-names = "default";
848*4882a593Smuzhiyun};
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun&pci1 {
851*4882a593Smuzhiyun	status = "okay";
852*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
853*4882a593Smuzhiyun	pinctrl-names = "default";
854*4882a593Smuzhiyun};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun&xhci {
857*4882a593Smuzhiyun	status = "okay";
858*4882a593Smuzhiyun	pinctrl-0 = <&usb2_pins>;
859*4882a593Smuzhiyun	pinctrl-names = "default";
860*4882a593Smuzhiyun};
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun&pci2 {
863*4882a593Smuzhiyun	status = "okay";
864*4882a593Smuzhiyun	pinctrl-0 = <&usb2_pins>;
865*4882a593Smuzhiyun	pinctrl-names = "default";
866*4882a593Smuzhiyun};
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun&hsusb {
869*4882a593Smuzhiyun	status = "okay";
870*4882a593Smuzhiyun	pinctrl-0 = <&hsusb_pins>;
871*4882a593Smuzhiyun	pinctrl-names = "default";
872*4882a593Smuzhiyun	renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
873*4882a593Smuzhiyun};
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun&usbphy {
876*4882a593Smuzhiyun	status = "okay";
877*4882a593Smuzhiyun};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun/* HDMI video input */
880*4882a593Smuzhiyun&vin0 {
881*4882a593Smuzhiyun	pinctrl-0 = <&vin0_pins>;
882*4882a593Smuzhiyun	pinctrl-names = "default";
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun	status = "okay";
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun	port {
887*4882a593Smuzhiyun		vin0ep2: endpoint {
888*4882a593Smuzhiyun			remote-endpoint = <&adv7612_out>;
889*4882a593Smuzhiyun			bus-width = <24>;
890*4882a593Smuzhiyun			hsync-active = <0>;
891*4882a593Smuzhiyun			vsync-active = <0>;
892*4882a593Smuzhiyun			pclk-sample = <1>;
893*4882a593Smuzhiyun			data-active = <1>;
894*4882a593Smuzhiyun		};
895*4882a593Smuzhiyun	};
896*4882a593Smuzhiyun};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun/* composite video input */
899*4882a593Smuzhiyun&vin1 {
900*4882a593Smuzhiyun	pinctrl-0 = <&vin1_pins>;
901*4882a593Smuzhiyun	pinctrl-names = "default";
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun	status = "okay";
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun	port {
906*4882a593Smuzhiyun		vin1ep0: endpoint {
907*4882a593Smuzhiyun			remote-endpoint = <&adv7180>;
908*4882a593Smuzhiyun			bus-width = <8>;
909*4882a593Smuzhiyun		};
910*4882a593Smuzhiyun	};
911*4882a593Smuzhiyun};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun&rcar_sound {
914*4882a593Smuzhiyun	pinctrl-0 = <&sound_pins &sound_clk_pins>;
915*4882a593Smuzhiyun	pinctrl-names = "default";
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun	/* Single DAI */
918*4882a593Smuzhiyun	#sound-dai-cells = <0>;
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun	status = "okay";
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun	rcar_sound,dai {
923*4882a593Smuzhiyun		dai0 {
924*4882a593Smuzhiyun			playback = <&ssi0 &src2 &dvc0>;
925*4882a593Smuzhiyun			capture  = <&ssi1 &src3 &dvc1>;
926*4882a593Smuzhiyun		};
927*4882a593Smuzhiyun	};
928*4882a593Smuzhiyun};
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun&rwdt {
931*4882a593Smuzhiyun	timeout-sec = <60>;
932*4882a593Smuzhiyun	status = "okay";
933*4882a593Smuzhiyun};
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun&ssi1 {
936*4882a593Smuzhiyun	shared-pin;
937*4882a593Smuzhiyun};
938