1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the R-Car H1 (R8A77790) Marzen board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Renesas Solutions Corp. 6*4882a593Smuzhiyun * Copyright (C) 2013 Simon Horman 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "r8a7779.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 12*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "marzen"; 16*4882a593Smuzhiyun compatible = "renesas,marzen", "renesas,r8a7779"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun aliases { 19*4882a593Smuzhiyun serial0 = &scif2; 20*4882a593Smuzhiyun serial1 = &scif4; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 25*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun memory@60000000 { 29*4882a593Smuzhiyun device_type = "memory"; 30*4882a593Smuzhiyun reg = <0x60000000 0x40000000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun fixedregulator3v3: regulator-3v3 { 34*4882a593Smuzhiyun compatible = "regulator-fixed"; 35*4882a593Smuzhiyun regulator-name = "fixed-3.3V"; 36*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 38*4882a593Smuzhiyun regulator-boot-on; 39*4882a593Smuzhiyun regulator-always-on; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun vccq_sdhi0: regulator-vccq-sdhi0 { 43*4882a593Smuzhiyun compatible = "regulator-gpio"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun regulator-name = "SDHI0 VccQ"; 46*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 47*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 50*4882a593Smuzhiyun gpios-states = <1>; 51*4882a593Smuzhiyun states = <3300000 1>, <1800000 0>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ethernet@18000000 { 55*4882a593Smuzhiyun compatible = "smsc,lan9220", "smsc,lan9115"; 56*4882a593Smuzhiyun reg = <0x18000000 0x100>; 57*4882a593Smuzhiyun pinctrl-0 = <ðernet_pins>; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun phy-mode = "mii"; 61*4882a593Smuzhiyun interrupt-parent = <&irqpin0>; 62*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 63*4882a593Smuzhiyun smsc,irq-push-pull; 64*4882a593Smuzhiyun reg-io-width = <4>; 65*4882a593Smuzhiyun vddvario-supply = <&fixedregulator3v3>; 66*4882a593Smuzhiyun vdd33a-supply = <&fixedregulator3v3>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun leds { 70*4882a593Smuzhiyun compatible = "gpio-leds"; 71*4882a593Smuzhiyun led2 { 72*4882a593Smuzhiyun gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun led3 { 75*4882a593Smuzhiyun gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun led4 { 78*4882a593Smuzhiyun gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun vga-encoder { 83*4882a593Smuzhiyun compatible = "adi,adv7123"; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun ports { 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun port@0 { 90*4882a593Smuzhiyun reg = <0>; 91*4882a593Smuzhiyun vga_enc_in: endpoint { 92*4882a593Smuzhiyun remote-endpoint = <&du_out_rgb0>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun port@1 { 96*4882a593Smuzhiyun reg = <1>; 97*4882a593Smuzhiyun vga_enc_out: endpoint { 98*4882a593Smuzhiyun remote-endpoint = <&vga_in>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun vga { 105*4882a593Smuzhiyun compatible = "vga-connector"; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun port { 108*4882a593Smuzhiyun vga_in: endpoint { 109*4882a593Smuzhiyun remote-endpoint = <&vga_enc_out>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun lvds-encoder { 115*4882a593Smuzhiyun compatible = "thine,thc63lvdm83d"; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun ports { 118*4882a593Smuzhiyun #address-cells = <1>; 119*4882a593Smuzhiyun #size-cells = <0>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun port@0 { 122*4882a593Smuzhiyun reg = <0>; 123*4882a593Smuzhiyun lvds_enc_in: endpoint { 124*4882a593Smuzhiyun remote-endpoint = <&du_out_rgb1>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun port@1 { 128*4882a593Smuzhiyun reg = <1>; 129*4882a593Smuzhiyun lvds_connector: endpoint { 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun x3_clk: x3-clock { 136*4882a593Smuzhiyun compatible = "fixed-clock"; 137*4882a593Smuzhiyun #clock-cells = <0>; 138*4882a593Smuzhiyun clock-frequency = <65000000>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&du { 143*4882a593Smuzhiyun pinctrl-0 = <&du_pins>; 144*4882a593Smuzhiyun pinctrl-names = "default"; 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; 148*4882a593Smuzhiyun clock-names = "du.0", "dclkin.0"; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun ports { 151*4882a593Smuzhiyun port@0 { 152*4882a593Smuzhiyun endpoint { 153*4882a593Smuzhiyun remote-endpoint = <&vga_enc_in>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun port@1 { 157*4882a593Smuzhiyun endpoint { 158*4882a593Smuzhiyun remote-endpoint = <&lvds_enc_in>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&irqpin0 { 165*4882a593Smuzhiyun status = "okay"; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&extal_clk { 169*4882a593Smuzhiyun clock-frequency = <31250000>; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&tmu0 { 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&pfc { 177*4882a593Smuzhiyun pinctrl-0 = <&scif_clk_pins>; 178*4882a593Smuzhiyun pinctrl-names = "default"; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun du_pins: du { 181*4882a593Smuzhiyun du0 { 182*4882a593Smuzhiyun groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; 183*4882a593Smuzhiyun function = "du0"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun du1 { 186*4882a593Smuzhiyun groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; 187*4882a593Smuzhiyun function = "du1"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun scif_clk_pins: scif_clk { 192*4882a593Smuzhiyun groups = "scif_clk_b"; 193*4882a593Smuzhiyun function = "scif_clk"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun ethernet_pins: ethernet { 197*4882a593Smuzhiyun intc { 198*4882a593Smuzhiyun groups = "intc_irq1_b"; 199*4882a593Smuzhiyun function = "intc"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun lbsc { 202*4882a593Smuzhiyun groups = "lbsc_ex_cs0"; 203*4882a593Smuzhiyun function = "lbsc"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun scif2_pins: scif2 { 208*4882a593Smuzhiyun groups = "scif2_data_c"; 209*4882a593Smuzhiyun function = "scif2"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun scif4_pins: scif4 { 213*4882a593Smuzhiyun groups = "scif4_data"; 214*4882a593Smuzhiyun function = "scif4"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun sdhi0_pins: sd0 { 218*4882a593Smuzhiyun groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; 219*4882a593Smuzhiyun function = "sdhi0"; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun hspi0_pins: hspi0 { 223*4882a593Smuzhiyun groups = "hspi0"; 224*4882a593Smuzhiyun function = "hspi0"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&sata { 229*4882a593Smuzhiyun status = "okay"; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun&scif2 { 233*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 234*4882a593Smuzhiyun pinctrl-names = "default"; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&scif4 { 240*4882a593Smuzhiyun pinctrl-0 = <&scif4_pins>; 241*4882a593Smuzhiyun pinctrl-names = "default"; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun status = "okay"; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&scif_clk { 247*4882a593Smuzhiyun clock-frequency = <14745600>; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun&sdhi0 { 251*4882a593Smuzhiyun pinctrl-0 = <&sdhi0_pins>; 252*4882a593Smuzhiyun pinctrl-names = "default"; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun vmmc-supply = <&fixedregulator3v3>; 255*4882a593Smuzhiyun vqmmc-supply = <&vccq_sdhi0>; 256*4882a593Smuzhiyun bus-width = <4>; 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun&hspi0 { 261*4882a593Smuzhiyun pinctrl-0 = <&hspi0_pins>; 262*4882a593Smuzhiyun pinctrl-names = "default"; 263*4882a593Smuzhiyun status = "okay"; 264*4882a593Smuzhiyun}; 265