1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter 4*4882a593Smuzhiyun * board 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2017 Renesas Electronics Corp. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "r8a7745-iwg22d-sodimm.dts" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; 13*4882a593Smuzhiyun compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial0 = &scif1; 17*4882a593Smuzhiyun serial4 = &scif5; 18*4882a593Smuzhiyun serial6 = &hscif2; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cec_clock: cec-clock { 22*4882a593Smuzhiyun compatible = "fixed-clock"; 23*4882a593Smuzhiyun #clock-cells = <0>; 24*4882a593Smuzhiyun clock-frequency = <12000000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun hdmi-out { 28*4882a593Smuzhiyun compatible = "hdmi-connector"; 29*4882a593Smuzhiyun type = "a"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun port { 32*4882a593Smuzhiyun hdmi_con: endpoint { 33*4882a593Smuzhiyun remote-endpoint = <&adv7511_out>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&du { 40*4882a593Smuzhiyun pinctrl-0 = <&du0_pins>; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun ports { 46*4882a593Smuzhiyun port@0 { 47*4882a593Smuzhiyun endpoint { 48*4882a593Smuzhiyun remote-endpoint = <&adv7511_in>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&can1 { 55*4882a593Smuzhiyun pinctrl-0 = <&can1_pins>; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&hscif2 { 62*4882a593Smuzhiyun pinctrl-0 = <&hscif2_pins>; 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&i2c1 { 69*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 70*4882a593Smuzhiyun pinctrl-names = "default"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun clock-frequency = <400000>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun hdmi@39 { 76*4882a593Smuzhiyun compatible = "adi,adv7511w"; 77*4882a593Smuzhiyun reg = <0x39>; 78*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 79*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 80*4882a593Smuzhiyun clocks = <&cec_clock>; 81*4882a593Smuzhiyun clock-names = "cec"; 82*4882a593Smuzhiyun pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun adi,input-depth = <8>; 85*4882a593Smuzhiyun adi,input-colorspace = "rgb"; 86*4882a593Smuzhiyun adi,input-clock = "1x"; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun ports { 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun port@0 { 93*4882a593Smuzhiyun reg = <0>; 94*4882a593Smuzhiyun adv7511_in: endpoint { 95*4882a593Smuzhiyun remote-endpoint = <&du_out_rgb0>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun port@1 { 100*4882a593Smuzhiyun reg = <1>; 101*4882a593Smuzhiyun adv7511_out: endpoint { 102*4882a593Smuzhiyun remote-endpoint = <&hdmi_con>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&lcd_panel { 110*4882a593Smuzhiyun status = "disabled"; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /delete-node/ port; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&pfc { 116*4882a593Smuzhiyun can1_pins: can1 { 117*4882a593Smuzhiyun groups = "can1_data_b"; 118*4882a593Smuzhiyun function = "can1"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun du0_pins: du0 { 122*4882a593Smuzhiyun groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; 123*4882a593Smuzhiyun function = "du0"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun hscif2_pins: hscif2 { 127*4882a593Smuzhiyun groups = "hscif2_data"; 128*4882a593Smuzhiyun function = "hscif2"; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun i2c1_pins: i2c1 { 132*4882a593Smuzhiyun groups = "i2c1_d"; 133*4882a593Smuzhiyun function = "i2c1"; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun scif1_pins: scif1 { 137*4882a593Smuzhiyun groups = "scif1_data"; 138*4882a593Smuzhiyun function = "scif1"; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun scif5_pins: scif5 { 142*4882a593Smuzhiyun groups = "scif5_data_d"; 143*4882a593Smuzhiyun function = "scif5"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&scif1 { 148*4882a593Smuzhiyun pinctrl-0 = <&scif1_pins>; 149*4882a593Smuzhiyun pinctrl-names = "default"; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&scif5 { 155*4882a593Smuzhiyun pinctrl-0 = <&scif5_pins>; 156*4882a593Smuzhiyun pinctrl-names = "default"; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun status = "okay"; 159*4882a593Smuzhiyun}; 160