1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the iWave RZ/G1H Qseven SOM 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "r8a7742.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "iwave,g21m", "renesas,r8a7742"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@40000000 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0 0x40000000 0 0x40000000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@200000000 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <2 0x00000000 0 0x40000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg_3p3v: 3p3v { 25*4882a593Smuzhiyun compatible = "regulator-fixed"; 26*4882a593Smuzhiyun regulator-name = "3P3V"; 27*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 28*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 29*4882a593Smuzhiyun regulator-always-on; 30*4882a593Smuzhiyun regulator-boot-on; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&extal_clk { 35*4882a593Smuzhiyun clock-frequency = <20000000>; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&gpio0 { 39*4882a593Smuzhiyun /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ 40*4882a593Smuzhiyun qspi_en { 41*4882a593Smuzhiyun gpio-hog; 42*4882a593Smuzhiyun gpios = <18 GPIO_ACTIVE_HIGH>; 43*4882a593Smuzhiyun output-low; 44*4882a593Smuzhiyun line-name = "QSPI_EN"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&i2c0 { 49*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 50*4882a593Smuzhiyun pinctrl-names = "default"; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun clock-frequency = <400000>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun rtc@68 { 56*4882a593Smuzhiyun compatible = "ti,bq32000"; 57*4882a593Smuzhiyun reg = <0x68>; 58*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 59*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&mmcif1 { 64*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 68*4882a593Smuzhiyun bus-width = <4>; 69*4882a593Smuzhiyun non-removable; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&pfc { 74*4882a593Smuzhiyun i2c0_pins: i2c0 { 75*4882a593Smuzhiyun groups = "i2c0"; 76*4882a593Smuzhiyun function = "i2c0"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun mmc1_pins: mmc1 { 80*4882a593Smuzhiyun groups = "mmc1_data4", "mmc1_ctrl"; 81*4882a593Smuzhiyun function = "mmc1"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun qspi_pins: qspi { 85*4882a593Smuzhiyun groups = "qspi_ctrl", "qspi_data2"; 86*4882a593Smuzhiyun function = "qspi"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&qspi { 91*4882a593Smuzhiyun pinctrl-0 = <&qspi_pins>; 92*4882a593Smuzhiyun pinctrl-names = "default"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun flash: flash@0 { 97*4882a593Smuzhiyun compatible = "sst,sst25vf016b", "jedec,spi-nor"; 98*4882a593Smuzhiyun reg = <0>; 99*4882a593Smuzhiyun spi-max-frequency = <50000000>; 100*4882a593Smuzhiyun m25p,fast-read; 101*4882a593Smuzhiyun spi-cpol; 102*4882a593Smuzhiyun spi-cpha; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun partitions { 105*4882a593Smuzhiyun compatible = "fixed-partitions"; 106*4882a593Smuzhiyun #address-cells = <1>; 107*4882a593Smuzhiyun #size-cells = <1>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun partition@0 { 110*4882a593Smuzhiyun label = "bootloader"; 111*4882a593Smuzhiyun reg = <0x00000000 0x000c0000>; 112*4882a593Smuzhiyun read-only; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun partition@c0000 { 115*4882a593Smuzhiyun label = "env"; 116*4882a593Smuzhiyun reg = <0x000c0000 0x00002000>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun partition@c2000 { 119*4882a593Smuzhiyun label = "user"; 120*4882a593Smuzhiyun reg = <0x000c2000 0x0013e000>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125