1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the iWave-RZ/G1H Qseven board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/* 9*4882a593Smuzhiyun * SSI-SGTL5000 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This command is required when Playback/Capture 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * amixer set "DVC Out" 100% 14*4882a593Smuzhiyun * amixer set "DVC In" 100% 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * You can use Mute 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * amixer set "DVC Out Mute" on 19*4882a593Smuzhiyun * amixer set "DVC In Mute" on 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * You can use Volume Ramp 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" 24*4882a593Smuzhiyun * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" 25*4882a593Smuzhiyun * amixer set "DVC Out Ramp" on 26*4882a593Smuzhiyun * aplay xxx.wav & 27*4882a593Smuzhiyun * amixer set "DVC Out" 80% // Volume Down 28*4882a593Smuzhiyun * amixer set "DVC Out" 100% // Volume Up 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/dts-v1/; 32*4882a593Smuzhiyun#include "r8a7742-iwg21m.dtsi" 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun/ { 35*4882a593Smuzhiyun model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; 36*4882a593Smuzhiyun compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun aliases { 39*4882a593Smuzhiyun serial2 = &scifa2; 40*4882a593Smuzhiyun serial4 = &scifb2; 41*4882a593Smuzhiyun ethernet0 = &avb; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun chosen { 45*4882a593Smuzhiyun bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; 46*4882a593Smuzhiyun stdout-path = "serial2:115200n8"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun audio_clock: audio_clock { 50*4882a593Smuzhiyun compatible = "fixed-clock"; 51*4882a593Smuzhiyun #clock-cells = <0>; 52*4882a593Smuzhiyun clock-frequency = <26000000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun leds { 56*4882a593Smuzhiyun compatible = "gpio-leds"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun sdhi2_led { 59*4882a593Smuzhiyun label = "sdio-led"; 60*4882a593Smuzhiyun gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; 61*4882a593Smuzhiyun linux,default-trigger = "mmc1"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun reg_1p5v: 1p5v { 66*4882a593Smuzhiyun compatible = "regulator-fixed"; 67*4882a593Smuzhiyun regulator-name = "1P5V"; 68*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 69*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 70*4882a593Smuzhiyun regulator-always-on; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun rsnd_sgtl5000: sound { 74*4882a593Smuzhiyun compatible = "simple-audio-card"; 75*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 76*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sndcodec>; 77*4882a593Smuzhiyun simple-audio-card,frame-master = <&sndcodec>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun sndcpu: simple-audio-card,cpu { 80*4882a593Smuzhiyun sound-dai = <&rcar_sound>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun sndcodec: simple-audio-card,codec { 84*4882a593Smuzhiyun sound-dai = <&sgtl5000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun vcc_sdhi2: regulator-vcc-sdhi2 { 89*4882a593Smuzhiyun compatible = "regulator-fixed"; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun regulator-name = "SDHI2 Vcc"; 92*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 93*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun vccq_sdhi2: regulator-vccq-sdhi2 { 99*4882a593Smuzhiyun compatible = "regulator-gpio"; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun regulator-name = "SDHI2 VccQ"; 102*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 103*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 106*4882a593Smuzhiyun gpios-states = <1>; 107*4882a593Smuzhiyun states = <3300000 1>, <1800000 0>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&avb { 112*4882a593Smuzhiyun pinctrl-0 = <&avb_pins>; 113*4882a593Smuzhiyun pinctrl-names = "default"; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun phy-handle = <&phy3>; 116*4882a593Smuzhiyun phy-mode = "gmii"; 117*4882a593Smuzhiyun renesas,no-ether-link; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun phy3: ethernet-phy@3 { 121*4882a593Smuzhiyun reg = <3>; 122*4882a593Smuzhiyun micrel,led-mode = <1>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&i2c2 { 127*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 128*4882a593Smuzhiyun pinctrl-names = "default"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun clock-frequency = <400000>; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun sgtl5000: codec@a { 134*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 135*4882a593Smuzhiyun #sound-dai-cells = <0>; 136*4882a593Smuzhiyun reg = <0x0a>; 137*4882a593Smuzhiyun clocks = <&audio_clock>; 138*4882a593Smuzhiyun VDDA-supply = <®_3p3v>; 139*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 140*4882a593Smuzhiyun VDDD-supply = <®_1p5v>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&can1 { 145*4882a593Smuzhiyun pinctrl-0 = <&can1_pins>; 146*4882a593Smuzhiyun pinctrl-names = "default"; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&cmt0 { 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&gpio1 { 156*4882a593Smuzhiyun can-trx-en-gpio{ 157*4882a593Smuzhiyun gpio-hog; 158*4882a593Smuzhiyun gpios = <28 GPIO_ACTIVE_HIGH>; 159*4882a593Smuzhiyun output-low; 160*4882a593Smuzhiyun line-name = "can-trx-en-gpio"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&hsusb { 165*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 166*4882a593Smuzhiyun pinctrl-names = "default"; 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&msiof0 { 171*4882a593Smuzhiyun pinctrl-0 = <&msiof0_pins>; 172*4882a593Smuzhiyun pinctrl-names = "default"; 173*4882a593Smuzhiyun cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun flash1: flash@0 { 178*4882a593Smuzhiyun compatible = "sst,sst25vf016b", "jedec,spi-nor"; 179*4882a593Smuzhiyun reg = <0>; 180*4882a593Smuzhiyun spi-max-frequency = <50000000>; 181*4882a593Smuzhiyun m25p,fast-read; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun partitions { 184*4882a593Smuzhiyun compatible = "fixed-partitions"; 185*4882a593Smuzhiyun #address-cells = <1>; 186*4882a593Smuzhiyun #size-cells = <1>; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun partition@0 { 189*4882a593Smuzhiyun label = "user"; 190*4882a593Smuzhiyun reg = <0x00000000 0x00200000>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&pci0 { 197*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 198*4882a593Smuzhiyun pinctrl-names = "default"; 199*4882a593Smuzhiyun /* Disable hsusb to enable USB2.0 host mode support on J2 */ 200*4882a593Smuzhiyun /* status = "okay"; */ 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&pci1 { 204*4882a593Smuzhiyun pinctrl-0 = <&usb1_pins>; 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun status = "okay"; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&pci2 { 210*4882a593Smuzhiyun /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ 211*4882a593Smuzhiyun /* status = "okay"; */ 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&pcie_bus_clk { 215*4882a593Smuzhiyun clock-frequency = <100000000>; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&pciec { 219*4882a593Smuzhiyun /* SW2[6] determines which connector is activated 220*4882a593Smuzhiyun * ON = PCIe X4 (connector-J7) 221*4882a593Smuzhiyun * OFF = mini-PCIe (connector-J26) 222*4882a593Smuzhiyun */ 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&pfc { 227*4882a593Smuzhiyun avb_pins: avb { 228*4882a593Smuzhiyun groups = "avb_mdio", "avb_gmii"; 229*4882a593Smuzhiyun function = "avb"; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun can1_pins: can1 { 233*4882a593Smuzhiyun groups = "can1_data_b"; 234*4882a593Smuzhiyun function = "can1"; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun i2c2_pins: i2c2 { 238*4882a593Smuzhiyun groups = "i2c2_b"; 239*4882a593Smuzhiyun function = "i2c2"; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun msiof0_pins: msiof0 { 243*4882a593Smuzhiyun groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; 244*4882a593Smuzhiyun function = "msiof0"; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun scifa2_pins: scifa2 { 248*4882a593Smuzhiyun groups = "scifa2_data_c"; 249*4882a593Smuzhiyun function = "scifa2"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun scifb2_pins: scifb2 { 253*4882a593Smuzhiyun groups = "scifb2_data", "scifb2_ctrl"; 254*4882a593Smuzhiyun function = "scifb2"; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun sdhi2_pins: sd2 { 258*4882a593Smuzhiyun groups = "sdhi2_data4", "sdhi2_ctrl"; 259*4882a593Smuzhiyun function = "sdhi2"; 260*4882a593Smuzhiyun power-source = <3300>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun sdhi2_pins_uhs: sd2_uhs { 264*4882a593Smuzhiyun groups = "sdhi2_data4", "sdhi2_ctrl"; 265*4882a593Smuzhiyun function = "sdhi2"; 266*4882a593Smuzhiyun power-source = <1800>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun sound_pins: sound { 270*4882a593Smuzhiyun groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; 271*4882a593Smuzhiyun function = "ssi"; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun usb0_pins: usb0 { 275*4882a593Smuzhiyun groups = "usb0"; 276*4882a593Smuzhiyun function = "usb0"; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun usb1_pins: usb1 { 280*4882a593Smuzhiyun groups = "usb1_pwen"; 281*4882a593Smuzhiyun function = "usb1"; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun}; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun&rcar_sound { 286*4882a593Smuzhiyun pinctrl-0 = <&sound_pins>; 287*4882a593Smuzhiyun pinctrl-names = "default"; 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* Single DAI */ 291*4882a593Smuzhiyun #sound-dai-cells = <0>; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun rcar_sound,dai { 294*4882a593Smuzhiyun dai0 { 295*4882a593Smuzhiyun playback = <&ssi4 &src4 &dvc1>; 296*4882a593Smuzhiyun capture = <&ssi3 &src3 &dvc0>; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&rwdt { 302*4882a593Smuzhiyun timeout-sec = <60>; 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&scifa2 { 307*4882a593Smuzhiyun pinctrl-0 = <&scifa2_pins>; 308*4882a593Smuzhiyun pinctrl-names = "default"; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun status = "okay"; 311*4882a593Smuzhiyun}; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun&scifb2 { 314*4882a593Smuzhiyun pinctrl-0 = <&scifb2_pins>; 315*4882a593Smuzhiyun pinctrl-names = "default"; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun uart-has-rtscts; 318*4882a593Smuzhiyun status = "okay"; 319*4882a593Smuzhiyun}; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun&sdhi2 { 322*4882a593Smuzhiyun pinctrl-0 = <&sdhi2_pins>; 323*4882a593Smuzhiyun pinctrl-1 = <&sdhi2_pins_uhs>; 324*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun vmmc-supply = <&vcc_sdhi2>; 327*4882a593Smuzhiyun vqmmc-supply = <&vccq_sdhi2>; 328*4882a593Smuzhiyun cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 329*4882a593Smuzhiyun wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 330*4882a593Smuzhiyun sd-uhs-sdr50; 331*4882a593Smuzhiyun status = "okay"; 332*4882a593Smuzhiyun}; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun&ssi4 { 335*4882a593Smuzhiyun shared-pin; 336*4882a593Smuzhiyun}; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun&usbphy { 339*4882a593Smuzhiyun status = "okay"; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&xhci { 343*4882a593Smuzhiyun status = "okay"; 344*4882a593Smuzhiyun}; 345