1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the iWave-RZ/G1H Qseven board development 4*4882a593Smuzhiyun * platform with camera daughter board 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "r8a7742-iwg21d-q7.dts" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; 14*4882a593Smuzhiyun compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun serial0 = &scif0; 18*4882a593Smuzhiyun serial1 = &scif1; 19*4882a593Smuzhiyun serial3 = &scifb1; 20*4882a593Smuzhiyun serial5 = &hscif0; 21*4882a593Smuzhiyun ethernet1 = ðer; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&avb { 26*4882a593Smuzhiyun /* Pins shared with VIN0, keep status disabled */ 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&can0 { 31*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunðer { 37*4882a593Smuzhiyun pinctrl-0 = <ðer_pins>; 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun phy-handle = <&phy1>; 41*4882a593Smuzhiyun renesas,ether-link-active-low; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun phy1: ethernet-phy@1 { 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun micrel,led-mode = <1>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&hscif0 { 51*4882a593Smuzhiyun pinctrl-0 = <&hscif0_pins>; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun uart-has-rtscts; 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&pfc { 58*4882a593Smuzhiyun can0_pins: can0 { 59*4882a593Smuzhiyun groups = "can0_data_d"; 60*4882a593Smuzhiyun function = "can0"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun ether_pins: ether { 64*4882a593Smuzhiyun groups = "eth_mdio", "eth_rmii"; 65*4882a593Smuzhiyun function = "eth"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun hscif0_pins: hscif0 { 69*4882a593Smuzhiyun groups = "hscif0_data", "hscif0_ctrl"; 70*4882a593Smuzhiyun function = "hscif0"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun scif0_pins: scif0 { 74*4882a593Smuzhiyun groups = "scif0_data"; 75*4882a593Smuzhiyun function = "scif0"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun scif1_pins: scif1 { 79*4882a593Smuzhiyun groups = "scif1_data"; 80*4882a593Smuzhiyun function = "scif1"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun scifb1_pins: scifb1 { 84*4882a593Smuzhiyun groups = "scifb1_data"; 85*4882a593Smuzhiyun function = "scifb1"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&scif0 { 90*4882a593Smuzhiyun pinctrl-0 = <&scif0_pins>; 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&scif1 { 96*4882a593Smuzhiyun pinctrl-0 = <&scif1_pins>; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&scifb1 { 102*4882a593Smuzhiyun pinctrl-0 = <&scifb1_pins>; 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun status = "okay"; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 107*4882a593Smuzhiyun cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 108*4882a593Smuzhiyun}; 109