xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r7s9210-rza2mevb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the RZA2MEVB board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun#include "r7s9210.dtsi"
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
13*4882a593Smuzhiyun#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "RZA2MEVB";
17*4882a593Smuzhiyun	compatible = "renesas,rza2mevb", "renesas,r7s9210";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		serial0 = &scif4;
21*4882a593Smuzhiyun		ethernet0 = &ether0;
22*4882a593Smuzhiyun		ethernet1 = &ether1;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	chosen {
26*4882a593Smuzhiyun		bootargs = "ignore_loglevel";
27*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	keyboard {
31*4882a593Smuzhiyun		compatible = "gpio-keys";
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		pinctrl-names = "default";
34*4882a593Smuzhiyun		pinctrl-0 = <&keyboard_pins>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		key-3 {
37*4882a593Smuzhiyun			interrupt-parent = <&irqc>;
38*4882a593Smuzhiyun			interrupts = <0 IRQ_TYPE_EDGE_BOTH>;
39*4882a593Smuzhiyun			linux,code = <KEY_3>;
40*4882a593Smuzhiyun			label = "SW3";
41*4882a593Smuzhiyun			wakeup-source;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	lbsc {
46*4882a593Smuzhiyun		#address-cells = <1>;
47*4882a593Smuzhiyun		#size-cells = <1>;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	leds {
51*4882a593Smuzhiyun		compatible = "gpio-leds";
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		red {
54*4882a593Smuzhiyun			gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun		green {
57*4882a593Smuzhiyun			gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	memory@40000000 {
62*4882a593Smuzhiyun		device_type = "memory";
63*4882a593Smuzhiyun		reg = <0x40000000 0x00800000>;	 /* HyperRAM */
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&ehci0 {
68*4882a593Smuzhiyun	status = "okay";
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&ehci1 {
72*4882a593Smuzhiyun	status = "okay";
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&ether0 {
76*4882a593Smuzhiyun	pinctrl-names = "default";
77*4882a593Smuzhiyun	pinctrl-0 = <&eth0_pins>;
78*4882a593Smuzhiyun	status = "okay";
79*4882a593Smuzhiyun	renesas,no-ether-link;
80*4882a593Smuzhiyun	phy-handle = <&phy0>;
81*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
82*4882a593Smuzhiyun		reg = <0>;
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&ether1 {
87*4882a593Smuzhiyun	pinctrl-names = "default";
88*4882a593Smuzhiyun	pinctrl-0 = <&eth1_pins>;
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun	renesas,no-ether-link;
91*4882a593Smuzhiyun	phy-handle = <&phy1>;
92*4882a593Smuzhiyun	phy1: ethernet-phy@1 {
93*4882a593Smuzhiyun		reg = <0>;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun/* EXTAL */
98*4882a593Smuzhiyun&extal_clk {
99*4882a593Smuzhiyun	clock-frequency = <24000000>;	/* 24MHz */
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun/* High resolution System tick timers */
103*4882a593Smuzhiyun&ostm0 {
104*4882a593Smuzhiyun	status = "okay";
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&ostm1 {
108*4882a593Smuzhiyun	status = "okay";
109*4882a593Smuzhiyun};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&pinctrl {
112*4882a593Smuzhiyun	eth0_pins: eth0 {
113*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
114*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
115*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
116*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
117*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
118*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
119*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
120*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
121*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
122*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
123*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	eth1_pins: eth1 {
127*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
128*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
129*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
130*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
131*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
132*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
133*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
134*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
135*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
136*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
137*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun	keyboard_pins: keyboard {
141*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>;	/* IRQ0 */
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun	/* Serial Console */
145*4882a593Smuzhiyun	scif4_pins: serial4 {
146*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORT9, 0, 4)>,	/* TxD4 */
147*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT9, 1, 4)>;	/* RxD4 */
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	sdhi0_pins: sdhi0 {
151*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORT5, 0, 3)>,	/* SD0_CD */
152*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT5, 1, 3)>;	/* SD0_WP */
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun	sdhi1_pins: sdhi1 {
156*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORT5, 4, 3)>,	/* SD1_CD */
157*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT5, 5, 3)>;	/* SD1_WP */
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	usb0_pins: usb0 {
161*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORT5, 2, 3)>,	/* VBUSIN0 */
162*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTC, 6, 1)>,	/* VBUSEN0 */
163*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTC, 7, 1)>;	/* OVRCUR0 */
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	usb1_pins: usb1 {
167*4882a593Smuzhiyun		pinmux = <RZA2_PINMUX(PORTC, 0, 1)>,	/* VBUSIN1 */
168*4882a593Smuzhiyun			 <RZA2_PINMUX(PORTC, 5, 1)>,	/* VBUSEN1 */
169*4882a593Smuzhiyun			 <RZA2_PINMUX(PORT7, 5, 5)>;	/* OVRCUR1 */
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun/* RTC_X1 */
174*4882a593Smuzhiyun&rtc_x1_clk {
175*4882a593Smuzhiyun	clock-frequency = <32768>;
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun/* Serial Console */
179*4882a593Smuzhiyun&scif4 {
180*4882a593Smuzhiyun	pinctrl-names = "default";
181*4882a593Smuzhiyun	pinctrl-0 = <&scif4_pins>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	status = "okay";
184*4882a593Smuzhiyun};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun&sdhi0 {
187*4882a593Smuzhiyun	pinctrl-names = "default";
188*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
189*4882a593Smuzhiyun	bus-width = <4>;
190*4882a593Smuzhiyun	status = "okay";
191*4882a593Smuzhiyun};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun&sdhi1 {
194*4882a593Smuzhiyun	pinctrl-names = "default";
195*4882a593Smuzhiyun	pinctrl-0 = <&sdhi1_pins>;
196*4882a593Smuzhiyun	bus-width = <4>;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun/* USB-0 as Host */
201*4882a593Smuzhiyun&usb2_phy0 {
202*4882a593Smuzhiyun	pinctrl-names = "default";
203*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
204*4882a593Smuzhiyun	dr_mode = "host";	/* Requires JP3 to be fitted */
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun/* USB-1 as Host */
209*4882a593Smuzhiyun&usb2_phy1 {
210*4882a593Smuzhiyun	pinctrl-names = "default";
211*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
212*4882a593Smuzhiyun	dr_mode = "host";
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun/* USB_X1 */
217*4882a593Smuzhiyun&usb_x1_clk {
218*4882a593Smuzhiyun	clock-frequency = <48000000>;
219*4882a593Smuzhiyun};
220