xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree Source for Sierra Wireless WP8548 Module
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016 BayLibre, SAS.
5*4882a593Smuzhiyun * Author : Neil Armstrong <narmstrong@baylibre.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
8*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
9*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
10*4882a593Smuzhiyun * whole.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
13*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
14*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
15*4882a593Smuzhiyun *     License, or (at your option) any later version.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
18*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
19*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20*4882a593Smuzhiyun *     GNU General Public License for more details.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Or, alternatively,
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
25*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
26*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
27*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
28*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
29*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
30*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
31*4882a593Smuzhiyun *     conditions:
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
34*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun#include "qcom-mdm9615.dtsi"
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/ {
49*4882a593Smuzhiyun	model = "Sierra Wireless WP8548 Module";
50*4882a593Smuzhiyun	compatible = "swir,wp8548", "qcom,mdm9615";
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	memory {
53*4882a593Smuzhiyun		device_type = "memory";
54*4882a593Smuzhiyun		reg = <0x48000000 0x7F00000>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&msmgpio {
59*4882a593Smuzhiyun	pinctrl-0 = <&reset_out_pins>;
60*4882a593Smuzhiyun	pinctrl-names = "default";
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	gsbi3_pins: gsbi3_pins {
63*4882a593Smuzhiyun		mux {
64*4882a593Smuzhiyun			pins = "gpio8", "gpio9", "gpio10", "gpio11";
65*4882a593Smuzhiyun			function = "gsbi3";
66*4882a593Smuzhiyun			drive-strength = <8>;
67*4882a593Smuzhiyun			bias-disable;
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	gsbi4_pins: gsbi4_pins {
72*4882a593Smuzhiyun		mux {
73*4882a593Smuzhiyun			pins = "gpio12", "gpio13", "gpio14", "gpio15";
74*4882a593Smuzhiyun			function = "gsbi4";
75*4882a593Smuzhiyun			drive-strength = <8>;
76*4882a593Smuzhiyun			bias-disable;
77*4882a593Smuzhiyun		};
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	gsbi5_i2c_pins: gsbi5_i2c_pins {
81*4882a593Smuzhiyun		pin16 {
82*4882a593Smuzhiyun			pins = "gpio16";
83*4882a593Smuzhiyun			function = "gsbi5_i2c";
84*4882a593Smuzhiyun			drive-strength = <8>;
85*4882a593Smuzhiyun			bias-disable;
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun		pin17 {
89*4882a593Smuzhiyun			pins = "gpio17";
90*4882a593Smuzhiyun			function = "gsbi5_i2c";
91*4882a593Smuzhiyun			drive-strength = <2>;
92*4882a593Smuzhiyun			bias-disable;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	gsbi5_uart_pins: gsbi5_uart_pins {
97*4882a593Smuzhiyun		mux {
98*4882a593Smuzhiyun			pins = "gpio18", "gpio19";
99*4882a593Smuzhiyun			function = "gsbi5_uart";
100*4882a593Smuzhiyun			drive-strength = <8>;
101*4882a593Smuzhiyun			bias-disable;
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	reset_out_pins: reset_out_pins {
106*4882a593Smuzhiyun		pins {
107*4882a593Smuzhiyun			pins = "gpio66";
108*4882a593Smuzhiyun			function = "gpio";
109*4882a593Smuzhiyun			drive-strength = <2>;
110*4882a593Smuzhiyun			bias-pull-up;
111*4882a593Smuzhiyun			output-high;
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun&pmicgpio {
117*4882a593Smuzhiyun	usb_vbus_5v_pins: usb_vbus_5v_pins {
118*4882a593Smuzhiyun		pins = "gpio4";
119*4882a593Smuzhiyun		function = "normal";
120*4882a593Smuzhiyun		output-high;
121*4882a593Smuzhiyun		bias-disable;
122*4882a593Smuzhiyun		qcom,drive-strength = <1>;
123*4882a593Smuzhiyun		power-source = <2>;
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&gsbi3 {
128*4882a593Smuzhiyun	status = "ok";
129*4882a593Smuzhiyun	qcom,mode = <GSBI_PROT_SPI>;
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&gsbi3_spi {
133*4882a593Smuzhiyun	status = "ok";
134*4882a593Smuzhiyun	pinctrl-0 = <&gsbi3_pins>;
135*4882a593Smuzhiyun	pinctrl-names = "default";
136*4882a593Smuzhiyun	assigned-clocks = <&gcc GSBI3_QUP_CLK>;
137*4882a593Smuzhiyun	assigned-clock-rates = <24000000>;
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&gsbi4 {
141*4882a593Smuzhiyun	status = "ok";
142*4882a593Smuzhiyun	qcom,mode = <GSBI_PROT_UART_W_FC>;
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&gsbi4_serial {
146*4882a593Smuzhiyun	status = "ok";
147*4882a593Smuzhiyun	pinctrl-0 = <&gsbi4_pins>;
148*4882a593Smuzhiyun	pinctrl-names = "default";
149*4882a593Smuzhiyun};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun&gsbi5 {
152*4882a593Smuzhiyun	status = "ok";
153*4882a593Smuzhiyun	qcom,mode = <GSBI_PROT_I2C_UART>;
154*4882a593Smuzhiyun};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun&gsbi5_i2c {
157*4882a593Smuzhiyun	status = "ok";
158*4882a593Smuzhiyun	clock-frequency = <200000>;
159*4882a593Smuzhiyun	pinctrl-0 = <&gsbi5_i2c_pins>;
160*4882a593Smuzhiyun	pinctrl-names = "default";
161*4882a593Smuzhiyun};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun&gsbi5_serial {
164*4882a593Smuzhiyun	status = "ok";
165*4882a593Smuzhiyun	pinctrl-0 = <&gsbi5_uart_pins>;
166*4882a593Smuzhiyun	pinctrl-names = "default";
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&sdcc1 {
170*4882a593Smuzhiyun	status = "ok";
171*4882a593Smuzhiyun};
172