xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun// Copyright (c) 2018, The Linux Foundation. All rights reserved.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include "qcom-ipq4019-ap.dk07.1.dtsi"
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
8*4882a593Smuzhiyun	compatible = "qcom,ipq4019-ap-dk07.1-c1";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	soc {
11*4882a593Smuzhiyun		pci@40000000 {
12*4882a593Smuzhiyun			status = "ok";
13*4882a593Smuzhiyun			perst-gpio = <&tlmm 38 0x1>;
14*4882a593Smuzhiyun		};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun		spi@78b6000 {
17*4882a593Smuzhiyun			status = "ok";
18*4882a593Smuzhiyun		};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun		pinctrl@1000000 {
21*4882a593Smuzhiyun			serial_1_pins: serial1-pinmux {
22*4882a593Smuzhiyun				pins = "gpio8", "gpio9",
23*4882a593Smuzhiyun					"gpio10", "gpio11";
24*4882a593Smuzhiyun				function = "blsp_uart1";
25*4882a593Smuzhiyun				bias-disable;
26*4882a593Smuzhiyun			};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun			spi_0_pins: spi-0-pinmux {
29*4882a593Smuzhiyun				pinmux {
30*4882a593Smuzhiyun					function = "blsp_spi0";
31*4882a593Smuzhiyun					pins = "gpio13", "gpio14", "gpio15";
32*4882a593Smuzhiyun					bias-disable;
33*4882a593Smuzhiyun				};
34*4882a593Smuzhiyun				pinmux_cs {
35*4882a593Smuzhiyun					function = "gpio";
36*4882a593Smuzhiyun					pins = "gpio12";
37*4882a593Smuzhiyun					bias-disable;
38*4882a593Smuzhiyun					output-high;
39*4882a593Smuzhiyun				};
40*4882a593Smuzhiyun			};
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		serial@78b0000 {
44*4882a593Smuzhiyun			pinctrl-0 = <&serial_1_pins>;
45*4882a593Smuzhiyun			pinctrl-names = "default";
46*4882a593Smuzhiyun			status = "ok";
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		spi@78b5000 {
50*4882a593Smuzhiyun			pinctrl-0 = <&spi_0_pins>;
51*4882a593Smuzhiyun			pinctrl-names = "default";
52*4882a593Smuzhiyun			status = "ok";
53*4882a593Smuzhiyun			cs-gpios = <&tlmm 12 0>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun			m25p80@0 {
56*4882a593Smuzhiyun				#address-cells = <1>;
57*4882a593Smuzhiyun				#size-cells = <1>;
58*4882a593Smuzhiyun				reg = <0>;
59*4882a593Smuzhiyun				compatible = "n25q128a11";
60*4882a593Smuzhiyun				spi-max-frequency = <24000000>;
61*4882a593Smuzhiyun			};
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun};
65