1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// Copyright (c) 2018, The Linux Foundation. All rights reserved. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "qcom-ipq4019.dtsi" 5*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun serial0 = &blsp1_uart1; 13*4882a593Smuzhiyun serial1 = &blsp1_uart2; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256MB */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun soc { 26*4882a593Smuzhiyun pinctrl@1000000 { 27*4882a593Smuzhiyun serial_0_pins: serial0-pinmux { 28*4882a593Smuzhiyun pins = "gpio16", "gpio17"; 29*4882a593Smuzhiyun function = "blsp_uart0"; 30*4882a593Smuzhiyun bias-disable; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun serial_1_pins: serial1-pinmux { 34*4882a593Smuzhiyun pins = "gpio8", "gpio9", 35*4882a593Smuzhiyun "gpio10", "gpio11"; 36*4882a593Smuzhiyun function = "blsp_uart1"; 37*4882a593Smuzhiyun bias-disable; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun spi_0_pins: spi-0-pinmux { 41*4882a593Smuzhiyun pinmux { 42*4882a593Smuzhiyun function = "blsp_spi0"; 43*4882a593Smuzhiyun pins = "gpio13", "gpio14", "gpio15"; 44*4882a593Smuzhiyun bias-disable; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun pinmux_cs { 47*4882a593Smuzhiyun function = "gpio"; 48*4882a593Smuzhiyun pins = "gpio12"; 49*4882a593Smuzhiyun bias-disable; 50*4882a593Smuzhiyun output-high; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun i2c_0_pins: i2c-0-pinmux { 55*4882a593Smuzhiyun pins = "gpio20", "gpio21"; 56*4882a593Smuzhiyun function = "blsp_i2c0"; 57*4882a593Smuzhiyun bias-disable; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun nand_pins: nand-pins { 61*4882a593Smuzhiyun pins = "gpio53", "gpio55", "gpio56", 62*4882a593Smuzhiyun "gpio57", "gpio58", "gpio59", 63*4882a593Smuzhiyun "gpio60", "gpio62", "gpio63", 64*4882a593Smuzhiyun "gpio64", "gpio65", "gpio66", 65*4882a593Smuzhiyun "gpio67", "gpio68", "gpio69"; 66*4882a593Smuzhiyun function = "qpic"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun serial@78af000 { 71*4882a593Smuzhiyun pinctrl-0 = <&serial_0_pins>; 72*4882a593Smuzhiyun pinctrl-names = "default"; 73*4882a593Smuzhiyun status = "ok"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun serial@78b0000 { 77*4882a593Smuzhiyun pinctrl-0 = <&serial_1_pins>; 78*4882a593Smuzhiyun pinctrl-names = "default"; 79*4882a593Smuzhiyun status = "ok"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun dma@7884000 { 83*4882a593Smuzhiyun status = "ok"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun spi@78b5000 { /* BLSP1 QUP1 */ 87*4882a593Smuzhiyun pinctrl-0 = <&spi_0_pins>; 88*4882a593Smuzhiyun pinctrl-names = "default"; 89*4882a593Smuzhiyun status = "ok"; 90*4882a593Smuzhiyun cs-gpios = <&tlmm 12 0>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun m25p80@0 { 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <1>; 95*4882a593Smuzhiyun reg = <0>; 96*4882a593Smuzhiyun compatible = "n25q128a11"; 97*4882a593Smuzhiyun spi-max-frequency = <24000000>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun pci@40000000 { 102*4882a593Smuzhiyun status = "ok"; 103*4882a593Smuzhiyun perst-gpio = <&tlmm 38 0x1>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun qpic-nand@79b0000 { 107*4882a593Smuzhiyun pinctrl-0 = <&nand_pins>; 108*4882a593Smuzhiyun pinctrl-names = "default"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112