1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "dt-bindings/clock/pxa-clock.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#define PMGROUP(pin) #pin 11*4882a593Smuzhiyun#define PMMUX(func, pin, af) \ 12*4882a593Smuzhiyun mux- ## func { \ 13*4882a593Smuzhiyun groups = PMGROUP(P ## pin); \ 14*4882a593Smuzhiyun function = #af; \ 15*4882a593Smuzhiyun } 16*4882a593Smuzhiyun#define PMMUX_LPM_LOW(func, pin, af) \ 17*4882a593Smuzhiyun mux- ## func { \ 18*4882a593Smuzhiyun groups = PMGROUP(P ## pin); \ 19*4882a593Smuzhiyun function = #af; \ 20*4882a593Smuzhiyun low-power-disable; \ 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun#define PMMUX_LPM_HIGH(func, pin, af) \ 23*4882a593Smuzhiyun mux- ## func { \ 24*4882a593Smuzhiyun groups = PMGROUP(P ## pin); \ 25*4882a593Smuzhiyun function = #af; \ 26*4882a593Smuzhiyun low-power-enable; \ 27*4882a593Smuzhiyun } 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun/ { 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <1>; 32*4882a593Smuzhiyun model = "Marvell PXA2xx family SoC"; 33*4882a593Smuzhiyun compatible = "marvell,pxa2xx"; 34*4882a593Smuzhiyun interrupt-parent = <&pxairq>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun aliases { 37*4882a593Smuzhiyun serial0 = &ffuart; 38*4882a593Smuzhiyun serial1 = &btuart; 39*4882a593Smuzhiyun serial2 = &stuart; 40*4882a593Smuzhiyun serial3 = &hwuart; 41*4882a593Smuzhiyun i2c0 = &pwri2c; 42*4882a593Smuzhiyun i2c1 = &pxai2c1; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun cpus { 46*4882a593Smuzhiyun cpu { 47*4882a593Smuzhiyun compatible = "marvell,xscale"; 48*4882a593Smuzhiyun device_type = "cpu"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pxabus { 53*4882a593Smuzhiyun compatible = "simple-bus"; 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <1>; 56*4882a593Smuzhiyun ranges; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun pxairq: interrupt-controller@40d00000 { 59*4882a593Smuzhiyun #interrupt-cells = <1>; 60*4882a593Smuzhiyun compatible = "marvell,pxa-intc"; 61*4882a593Smuzhiyun interrupt-controller; 62*4882a593Smuzhiyun interrupt-parent; 63*4882a593Smuzhiyun marvell,intc-nr-irqs = <32>; 64*4882a593Smuzhiyun reg = <0x40d00000 0xd0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun gpio: gpio@40e00000 { 68*4882a593Smuzhiyun compatible = "mrvl,pxa-gpio"; 69*4882a593Smuzhiyun #address-cells = <0x1>; 70*4882a593Smuzhiyun #size-cells = <0x1>; 71*4882a593Smuzhiyun reg = <0x40e00000 0x10000>; 72*4882a593Smuzhiyun gpio-controller; 73*4882a593Smuzhiyun #gpio-cells = <0x2>; 74*4882a593Smuzhiyun interrupts = <8>, <9>, <10>; 75*4882a593Smuzhiyun interrupt-names = "gpio0", "gpio1", "gpio_mux"; 76*4882a593Smuzhiyun interrupt-controller; 77*4882a593Smuzhiyun #interrupt-cells = <0x2>; 78*4882a593Smuzhiyun ranges; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun gcb0: gpio@40e00000 { 81*4882a593Smuzhiyun reg = <0x40e00000 0x4>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun gcb1: gpio@40e00004 { 85*4882a593Smuzhiyun reg = <0x40e00004 0x4>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun gcb2: gpio@40e00008 { 89*4882a593Smuzhiyun reg = <0x40e00008 0x4>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun gcb3: gpio@40e0000c { 92*4882a593Smuzhiyun reg = <0x40e0000c 0x4>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun ffuart: serial@40100000 { 97*4882a593Smuzhiyun compatible = "mrvl,pxa-uart"; 98*4882a593Smuzhiyun reg = <0x40100000 0x30>; 99*4882a593Smuzhiyun interrupts = <22>; 100*4882a593Smuzhiyun clocks = <&clks CLK_FFUART>; 101*4882a593Smuzhiyun status = "disabled"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun btuart: serial@40200000 { 105*4882a593Smuzhiyun compatible = "mrvl,pxa-uart"; 106*4882a593Smuzhiyun reg = <0x40200000 0x30>; 107*4882a593Smuzhiyun interrupts = <21>; 108*4882a593Smuzhiyun clocks = <&clks CLK_BTUART>; 109*4882a593Smuzhiyun status = "disabled"; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun stuart: serial@40700000 { 113*4882a593Smuzhiyun compatible = "mrvl,pxa-uart"; 114*4882a593Smuzhiyun reg = <0x40700000 0x30>; 115*4882a593Smuzhiyun interrupts = <20>; 116*4882a593Smuzhiyun clocks = <&clks CLK_STUART>; 117*4882a593Smuzhiyun status = "disabled"; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun hwuart: serial@41600000 { 121*4882a593Smuzhiyun compatible = "mrvl,pxa-uart"; 122*4882a593Smuzhiyun reg = <0x41600000 0x30>; 123*4882a593Smuzhiyun interrupts = <7>; 124*4882a593Smuzhiyun status = "disabled"; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun pxai2c1: i2c@40301680 { 128*4882a593Smuzhiyun compatible = "mrvl,pxa-i2c"; 129*4882a593Smuzhiyun reg = <0x40301680 0x30>; 130*4882a593Smuzhiyun interrupts = <18>; 131*4882a593Smuzhiyun clocks = <&clks CLK_I2C>; 132*4882a593Smuzhiyun #address-cells = <0x1>; 133*4882a593Smuzhiyun #size-cells = <0>; 134*4882a593Smuzhiyun status = "disabled"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun mmc0: mmc@41100000 { 138*4882a593Smuzhiyun compatible = "marvell,pxa-mmc"; 139*4882a593Smuzhiyun reg = <0x41100000 0x1000>; 140*4882a593Smuzhiyun interrupts = <23>; 141*4882a593Smuzhiyun clocks = <&clks CLK_MMC>; 142*4882a593Smuzhiyun dmas = <&pdma 21 3 143*4882a593Smuzhiyun &pdma 22 3>; 144*4882a593Smuzhiyun dma-names = "rx", "tx"; 145*4882a593Smuzhiyun status = "disabled"; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun rtc@40900000 { 149*4882a593Smuzhiyun compatible = "marvell,pxa-rtc"; 150*4882a593Smuzhiyun reg = <0x40900000 0x3c>; 151*4882a593Smuzhiyun interrupts = <30 31>; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun lcdc: lcd-controller@40500000 { 155*4882a593Smuzhiyun compatible = "marvell,pxa2xx-lcdc"; 156*4882a593Smuzhiyun reg = <0x44000000 0x10000>; 157*4882a593Smuzhiyun interrupts = <17>; 158*4882a593Smuzhiyun clocks = <&clks CLK_LCD>; 159*4882a593Smuzhiyun status = "disabled"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163