1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* The pxa3xx skeleton simply augments the 2xx version */ 3*4882a593Smuzhiyun#include "pxa2xx.dtsi" 4*4882a593Smuzhiyun#include "dt-bindings/clock/pxa-clock.h" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun model = "Marvell PXA27x familiy SoC"; 8*4882a593Smuzhiyun compatible = "marvell,pxa27x"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun pxabus { 11*4882a593Smuzhiyun pdma: dma-controller@40000000 { 12*4882a593Smuzhiyun compatible = "marvell,pdma-1.0"; 13*4882a593Smuzhiyun reg = <0x40000000 0x10000>; 14*4882a593Smuzhiyun interrupts = <25>; 15*4882a593Smuzhiyun #dma-channels = <32>; 16*4882a593Smuzhiyun #dma-cells = <2>; 17*4882a593Smuzhiyun #dma-requests = <75>; 18*4882a593Smuzhiyun status = "okay"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun pxairq: interrupt-controller@40d00000 { 22*4882a593Smuzhiyun marvell,intc-priority; 23*4882a593Smuzhiyun marvell,intc-nr-irqs = <34>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun pinctrl: pinctrl@40e00000 { 27*4882a593Smuzhiyun reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 28*4882a593Smuzhiyun 0x40f00020 0x10>; 29*4882a593Smuzhiyun compatible = "marvell,pxa27x-pinctrl"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun gpio: gpio@40e00000 { 33*4882a593Smuzhiyun compatible = "intel,pxa27x-gpio"; 34*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 128>; 35*4882a593Smuzhiyun clocks = <&clks CLK_NONE>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun usb0: usb@4c000000 { 39*4882a593Smuzhiyun compatible = "marvell,pxa-ohci"; 40*4882a593Smuzhiyun reg = <0x4c000000 0x10000>; 41*4882a593Smuzhiyun interrupts = <3>; 42*4882a593Smuzhiyun clocks = <&clks CLK_USBHOST>; 43*4882a593Smuzhiyun status = "disabled"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun pwm0: pwm@40b00000 { 47*4882a593Smuzhiyun compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 48*4882a593Smuzhiyun reg = <0x40b00000 0x10>; 49*4882a593Smuzhiyun #pwm-cells = <1>; 50*4882a593Smuzhiyun clocks = <&clks CLK_PWM0>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun pwm1: pwm@40b00010 { 54*4882a593Smuzhiyun compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 55*4882a593Smuzhiyun reg = <0x40b00010 0x10>; 56*4882a593Smuzhiyun #pwm-cells = <1>; 57*4882a593Smuzhiyun clocks = <&clks CLK_PWM1>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun pwm2: pwm@40c00000 { 61*4882a593Smuzhiyun compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 62*4882a593Smuzhiyun reg = <0x40c00000 0x10>; 63*4882a593Smuzhiyun #pwm-cells = <1>; 64*4882a593Smuzhiyun clocks = <&clks CLK_PWM0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pwm3: pwm@40c00010 { 68*4882a593Smuzhiyun compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 69*4882a593Smuzhiyun reg = <0x40c00010 0x10>; 70*4882a593Smuzhiyun #pwm-cells = <1>; 71*4882a593Smuzhiyun clocks = <&clks CLK_PWM1>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun pwri2c: i2c@40f00180 { 75*4882a593Smuzhiyun compatible = "mrvl,pxa-i2c"; 76*4882a593Smuzhiyun reg = <0x40f00180 0x24>; 77*4882a593Smuzhiyun interrupts = <6>; 78*4882a593Smuzhiyun clocks = <&clks CLK_PWRI2C>; 79*4882a593Smuzhiyun #address-cells = <0x1>; 80*4882a593Smuzhiyun #size-cells = <0>; 81*4882a593Smuzhiyun status = "disabled"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun pxa27x_udc: udc@40600000 { 85*4882a593Smuzhiyun compatible = "marvell,pxa270-udc"; 86*4882a593Smuzhiyun reg = <0x40600000 0x10000>; 87*4882a593Smuzhiyun interrupts = <11>; 88*4882a593Smuzhiyun clocks = <&clks CLK_USB>; 89*4882a593Smuzhiyun status = "disabled"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun keypad: keypad@41500000 { 93*4882a593Smuzhiyun compatible = "marvell,pxa27x-keypad"; 94*4882a593Smuzhiyun reg = <0x41500000 0x4c>; 95*4882a593Smuzhiyun interrupts = <4>; 96*4882a593Smuzhiyun clocks = <&clks CLK_KEYPAD>; 97*4882a593Smuzhiyun status = "disabled"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pxa_camera: imaging@50000000 { 101*4882a593Smuzhiyun compatible = "marvell,pxa270-qci"; 102*4882a593Smuzhiyun reg = <0x50000000 0x1000>; 103*4882a593Smuzhiyun interrupts = <33>; 104*4882a593Smuzhiyun dmas = <&pdma 68 0 /* Y channel */ 105*4882a593Smuzhiyun &pdma 69 0 /* U channel */ 106*4882a593Smuzhiyun &pdma 70 0>; /* V channel */ 107*4882a593Smuzhiyun dma-names = "CI_Y", "CI_U", "CI_V"; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun clocks = <&clks CLK_CAMERA>; 110*4882a593Smuzhiyun clock-names = "ciclk"; 111*4882a593Smuzhiyun clock-frequency = <5000000>; 112*4882a593Smuzhiyun clock-output-names = "qci_mclk"; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun status = "disabled"; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun rtc@40900000 { 118*4882a593Smuzhiyun clocks = <&clks CLK_OSC32k768>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun clocks { 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * The muxing of external clocks/internal dividers for osc* clock 125*4882a593Smuzhiyun * sources has been hidden under the carpet by now. 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #address-cells = <1>; 128*4882a593Smuzhiyun #size-cells = <1>; 129*4882a593Smuzhiyun ranges; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun clks: pxa2xx_clks@41300004 { 132*4882a593Smuzhiyun compatible = "marvell,pxa270-clocks"; 133*4882a593Smuzhiyun #clock-cells = <1>; 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun timer@40a00000 { 139*4882a593Smuzhiyun compatible = "marvell,pxa-timer"; 140*4882a593Smuzhiyun reg = <0x40a00000 0x20>; 141*4882a593Smuzhiyun interrupts = <26>; 142*4882a593Smuzhiyun clocks = <&clks CLK_OSTIMER>; 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun pxa270_opp_table: opp_table0 { 147*4882a593Smuzhiyun compatible = "operating-points-v2"; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun opp-104000000 { 150*4882a593Smuzhiyun opp-hz = /bits/ 64 <104000000>; 151*4882a593Smuzhiyun opp-microvolt = <900000 900000 1705000>; 152*4882a593Smuzhiyun clock-latency-ns = <20>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun opp-156000000 { 155*4882a593Smuzhiyun opp-hz = /bits/ 64 <156000000>; 156*4882a593Smuzhiyun opp-microvolt = <1000000 1000000 1705000>; 157*4882a593Smuzhiyun clock-latency-ns = <20>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun opp-208000000 { 160*4882a593Smuzhiyun opp-hz = /bits/ 64 <208000000>; 161*4882a593Smuzhiyun opp-microvolt = <1180000 1180000 1705000>; 162*4882a593Smuzhiyun clock-latency-ns = <20>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun opp-312000000 { 165*4882a593Smuzhiyun opp-hz = /bits/ 64 <312000000>; 166*4882a593Smuzhiyun opp-microvolt = <1250000 1250000 1705000>; 167*4882a593Smuzhiyun clock-latency-ns = <20>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun opp-416000000 { 170*4882a593Smuzhiyun opp-hz = /bits/ 64 <416000000>; 171*4882a593Smuzhiyun opp-microvolt = <1350000 1350000 1705000>; 172*4882a593Smuzhiyun clock-latency-ns = <20>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun opp-520000000 { 175*4882a593Smuzhiyun opp-hz = /bits/ 64 <520000000>; 176*4882a593Smuzhiyun opp-microvolt = <1450000 1450000 1705000>; 177*4882a593Smuzhiyun clock-latency-ns = <20>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun opp-624000000 { 180*4882a593Smuzhiyun opp-hz = /bits/ 64 <624000000>; 181*4882a593Smuzhiyun opp-microvolt = <1550000 1550000 1705000>; 182*4882a593Smuzhiyun clock-latency-ns = <20>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun}; 186